一句话：提出 Cider，利用高级硬件设计语言中的控制流信息，为编译到硬件的语言提供软件式逐步调试抽象。
高级硬件设计语言让领域专家能快速生成专用加速器，但调试工具仍绑定在低级 HDL 上，而高级描述中的控制流信息在 HDL 代码中已丢失。本文提出 Cider，一个逐步调试器，它基于保留控制信息的中间语言 Calyx，为编译到硬件的语言提供断点、观察点、状态检查和源码级位置映射等软件式调试抽象。作者通过一个新加速器生成器和两个已有生成器的案例研究，展示了 Cider 如何帮助发现并定位此前未报告的缺陷。由于直接模拟控制信息丰富的表示，Cider 避免在设计的非活跃部分浪费精力；尽管基本未优化，其性能仍可与开源 HDL 模拟器竞争。
High-level programming models for hardware design let domain experts quickly produce specialized accelerators. However, tools for debugging these accelerators remain tied to low-level hardware description languages (HDLs). High-level descriptions contain control-flow information that is lost in HDL code. We describe Cider, a stepwise debugger that exploits this information to provide software-like debugging abstractions for languages that compile to hardware. Cider uses Calyx, an intermediate language for accelerator generators that preserves control information. Cider provides breakpoints, watchpoints, state inspection, and source-level position mapping. Using case studies that examine one new and two preexisting accelerator generators, we demonstrate how Cider helps find and localize previously unreported bugs. By directly simulating a control-rich representation, Cider avoids wasting effort on inactive parts of the design and, despite being largely unoptimized, performs competitively with open-source HDL simulators.