一句话：提出算法与架构协同设计的硬件加速方案 DPACS，让动态剪枝的理论计算缩减真正转化为端到端加速。
动态剪枝（DP）能依据运行时输入智能地跳过计算操作，从而在不显著损失精度的前提下大幅提升深度神经网络推理速度。然而，已有 DP 算法虽具备良好的剪枝效果，把这些理论上的计算量缩减落地为实际系统中令人满意的端到端加速仍然困难。论文指出三大障碍：运行时识别待剪枝操作本身的开销、对由此产生的动态数据流的处理需求，以及随着计算操作减少而日益突出的内存 I/O 瓶颈。针对这些问题，作者提出 DPACS，采用算法-架构协同设计的方法，从算法与硬件架构两个层面联合优化，以降低动态剪枝的运行开销并缓解访存瓶颈。摘要未给出具体实验数据。
By eliminating compute operations intelligently based on the run time input, dynamic pruning (DP) promises to improve deep neural network inference speed substantially without incurring a major impact on their accuracy. Although many DP algorithms with good pruning performance have been proposed, it remains a challenge to translate these theoretical reductions in compute operations into satisfactory end-to-end speedups in practical real-world implementations. The overhead of identifying operations to be pruned during run time, the need to efficiently process the resulting dynamic dataflow, and the non-trivial memory I/O bottleneck that emerges as the number of compute operations reduces, have all contributed to the challenge of implementing practical DP systems.
@inproceedings{paperbot10050,
title = {DPACS: Hardware Accelerated Dynamic Neural Network Pruning through Algorithm-Architecture Co-design},
author = {Yizhao Gao and Baoheng Zhang and Xiaojuan Qi and Hayden Kwok-Hay So},
booktitle = {ASPLOS},
year = {2023},
doi = {10.1145/3575693.3575728}
}