一句话：APEX 用频繁子图挖掘从应用基准中提取常见计算子图，自动生成专用 CGRA 处理单元硬件与编译器，实现领域驱动的加速器设计空间探索。
粗粒度可重构阵列（CGRA）的处理单元（PE）架构显著影响其性能与能效，但手工设计耗时费力。APEX 提出自动化方法：先用频繁子图挖掘从领域基准中提取常见计算子图，再通过数据通路图合并算法将子图合并为专用 PE 数据通路；合并后的数据通路图被翻译为 PE 规约，进而自动生成 Verilog 硬件描述以及将应用映射到 PE 的编译器，并集成到灵活的 CGRA 生成与编译工具链中以实现快速评估。在图像处理和机器学习两个领域，相比通用 CGRA，自动生成 CGRA 的面积分别减少 5%–30% 和 22%–39%，能耗分别降低 22%–46% 和 16%–59%。该工作为应用领域驱动的设计空间探索框架铺平了道路，显著降低了硬件与编译器生成的设计工作量。
The architecture of a coarse-grained reconfigurable array (CGRA) processing element (PE) has a significant effect on the performance and energy-efficiency of an application running on the CGRA. This paper presents APEX, an automated approach for generating specialized PE architectures for an application or an application domain. APEX first analyzes application domain benchmarks using frequent subgraph mining to extract commonly occurring computational subgraphs. APEX then generates specialized PEs by merging subgraphs using a datapath graph merging algorithm. The merged datapath graphs are translated into a PE specification from which we automatically generate the PE hardware description in Verilog along with a compiler that maps applications to the PE. The PE hardware and compiler are inserted into a flexible CGRA generation and compilation toolchain that allows for agile evaluation of CGRAs. We evaluate APEX for two domains, machine learning and image processing. For image processing applications, our automatically generated CGRAs with specialized PEs achieve from 5% to 30% less area and from 22% to 46% less energy compared to a general-purpose CGRA. For machine learning applications, our automatically generated CGRAs consume 16% to 59% less energy and 22% to 39% less area than a general-purpose CGRA. This work paves the way for creation of application domain-driven design-space exploration frameworks that automatically generate efficient programmable accelerators, with a much lower design effort for both hardware and compiler generation.
@inproceedings{paperbot10053,
title = {APEX: A Framework for Automated Processing Element Design Space Exploration using Frequent Subgraph Analysis},
author = {Jackson Melchert and Kathleen Feng and Caleb Donovick and Ross Daly and Ritvik Sharma and Clark Barrett and Mark A. Horowitz and Pat Hanrahan and Priyanka Raina},
booktitle = {ASPLOS},
year = {2023},
doi = {10.1145/3582016.3582070}
}