一句话：提出空间高效的 TREC 优化，使 DNN 在微控制器上通过计算复用减少计算并保持精度。
在资源受限的微控制器上部署深度神经网络面临严格的空间和算力限制。本文研究如何使 TREC（一种为 DNN 引入计算复用的优化）在微控制器上兼具空间与时间效率。方法在保持 DNN 精度稳定的前提下最大化性能收益，对 TREC 进行空间高效化改造。实验表明，该方案可消除 DNN 中超过 96% 的计算，使模型能够适应微控制器，获得 3.4–5 倍加速且精度损失很小。
Deploying deep neural networks (DNNs) for a resource-constrained environment and achieving satisfactory performance is challenging. It is especially so on microcontrollers for their stringent space and computing power. This paper focuses on new ways to make TREC, an optimization recently proposed to enable computation reuse in DNNs, space and time efficient on Microcontrollers. The solution maximizes the performance benefits while keeping the DNN accuracy stable. Experiments show that the solution eliminates over 96% computations in DNNs and makes them fit well into microcontrollers, producing 3.4-5× speedups with only marginal accuracy loss.
@inproceedings{paperbot10062,
title = {Space-Efficient TREC for Enabling Deep Learning on Microcontrollers},
author = {Jiesong Liu and Feng Zhang and Jiawei Guan and Hsin-Hsuan Sung and Xiaoguang Guo and Xiaoyong Du and Xipeng Shen},
booktitle = {ASPLOS},
year = {2023},
doi = {10.1145/3582016.3582062}
}