一句话：Rosebud 通过标准化软硬件接口解耦 FPGA 加速器与软件包处理，简化中间盒开发、调试与性能调优。
设计 FPGA 加速的中间盒通常需要同时处理硬件加速器实现与软件应用逻辑，导致开发、调试和性能调优复杂。Rosebud 提出一种标准化硬件/软件接口，将硬件加速器接入高性能数据包处理流水线，从而解耦硬件实现与软件编程：硬件开发者可专注优化定制加速器，软件开发者则能以类似软件库的方式复用、配置和调试加速器。作者通过构建基于大黑名单的防火墙并在不到一个月内移植 Pigasus IDS 模式匹配加速器来验证该框架。实验表明，Rosebud 可提供约 200 Gbps 吞吐，同时仅增加 0.7–7 微秒延迟。
We introduce an approach to designing FPGA-accelerated middleboxes that simplifies development, debugging, and performance tuning by decoupling the tasks of hardware-accelerator implementation and software-application programming. Rosebud is a framework that links hardware accelerators to a high-performance packet processing pipeline through a standardized hardware/software interface. This separation of concerns allows hardware developers to focus on optimizing custom accelerators while freeing software programmers to reuse, configure, and debug accelerators in a fashion akin to software libraries. We show the benefits of the Rosebud framework by building a firewall based on a large blacklist and porting the Pigasus IDS pattern-matching accelerator in less than a month. Our experiments demonstrate that Rosebud delivers high performance, serving ∼200 Gbps of traffic while adding only 0.7–7 microseconds of latency.
@inproceedings{paperbot10095,
title = {Rosebud: Making FPGA-Accelerated Middlebox Development More Pleasant},
author = {Moein Khazraee and Alex Forencich and George C. Papen and Alex C. Snoeren and Aaron Schulman},
booktitle = {ASPLOS},
year = {2023},
doi = {10.1145/3582016.3582067}
}