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P2 eHDL: Turning eBPF/XDP Programs into Hardware Designs for the NIC

eHDL:将 eBPF/XDP 程序转化为面向 NIC 的硬件设计
ASPLOS Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 32023匹配度 2/10 · 该论文属于编译器/代码生成与体系结构交叉,将 eBPF/XDP 程序综合为 FPGA NIC 硬件流水线;与用户画像中的静态分析、LLM/Agent、浮点程序分析、贝叶斯程序分析等核心方向没有直接关联。引用 15 inbox
Alessandro Rivitti, Roberto Bifulco, Angelo Tulumello, Marco Bonola, Salvatore Pontarelli
crossref: 2026-09-12

AI 速览

一句话:提出 eHDL,从未修改的 eBPF/XDP 程序自动生成 FPGA NIC 硬件流水线。

网络包处理性能需利用设备硬件特性,但软件程序员需面对异构架构并重写软件。本文提出高层综合工具 eHDL,可将未修改的 Linux eBPF/XDP 程序自动转换为 NIC 硬件流水线,使无硬件经验的开发者也能定义有状态、作用于完整包数据的功能。作者在 Xilinx Alveo U50 FPGA NIC 上原型实现,用 5 个 eBPF/XDP 程序评估。生成流水线仅占 6.5%–13.3% FPGA 资源,转发达到线速且每包延迟约 1 微秒;相比基于处理器的 eBPF/XDP NIC 卸载方案,吞吐提高 10–100 倍。

问题
网络软件需要利用 NIC 硬件特性来扩展包处理性能,但设备架构异构且常需重写软件,令网络程序员难以直接定义所需硬件功能。
方法
提出 eHDL 高层综合工具,将未修改的 Linux eBPF/XDP 程序自动生成面向 NIC 的硬件流水线,并在 Xilinx Alveo U50 FPGA NIC 上实现原型。
评估
使用 5 个 eBPF/XDP 程序评估生成流水线的 FPGA 资源占用、转发吞吐与每包延迟,并与网络专用高层综合工具及基于处理器的 eBPF/XDP 卸载方案比较。
原文摘要(Abstract)

Scaling network packet processing performance to meet the increasing speed of network ports requires software programs to carefully leverage the network devices’ hardware features. This is a complex task for network programmers, who need to learn and deal with the heterogeneity of device architectures, and re-think their software to leverage them. In this paper we make first steps to reverse this design process, enabling the automatic generation of tailored hardware designs starting from a network packet processing program. We introduce eHDL, a high-level synthesis tool that automatically generates hardware pipelines from unmodified Linux’s eBPF/XDP programs. eHDL is designed to enable software developers to directly define and implement the hardware functions they need in the NIC. We prototype eHDL targeting a Xilinx Alveo U50 FPGA NIC, and evaluate it with a set of 5 eBPF/XDP programs. Our results show that the generated pipelines are efficient in terms of required hardware resources, using only 6.5%-13.3% of the FPGA, and always achieve the line rate forwarding throughput with about 1 microsecond of per-packet forwarding latency. Compared to other network-specific high-level synthesis tool, eHDL enables software programmers with no hardware expertise to describe stateful functions that operate on the entire packet data. Compared to alternative processor-based solutions that perform eBFP/XDP offloading to a NIC, eHDL provides 10-100x higher throughput.

链接与引用

DOI 原文 · PDF(开放获取) ·

BibTeX
@inproceedings{paperbot10097,
  title = {eHDL: Turning eBPF/XDP Programs into Hardware Designs for the NIC},
  author = {Alessandro Rivitti and Roberto Bifulco and Angelo Tulumello and Marco Bonola and Salvatore Pontarelli},
  booktitle = {ASPLOS},
  year = {2023},
  doi = {10.1145/3582016.3582035}
}