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P2 CaT: A Solver-Aided Compiler for Packet-Processing Pipelines

CaT:面向包处理流水线的求解器辅助编译器
ASPLOS Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 32023匹配度 3/10 · 论文属于PL领域的编译器与程序合成,使用求解器并面向工业可编程交换机,但未涉及用户核心关注的LLM/Agent、静态分析、浮点或贝叶斯程序分析,与研究方向匹配度低。引用 8 inbox
Xiangyu Gao, Divya Raghunathan, Ruijie Fang, Tao Wang, Xiaotong Zhu, Anirudh Sivaraman, Srinivas Narayana, Aarti Gupta
crossref: 2026-09-12

AI 速览

一句话:将包处理流水线编译分解为变换、综合、分配三阶段并借助求解器实现,生成代码更快且资源占用更少。

把高层程序编译到高速包处理流水线本质上是一个组合优化问题:编译器既要让流水线的资源配置符合程序高层规约的语义,又要把程序的全部计算塞进有限的流水线资源中。已有工作只针对该问题的某个侧面,难以在可接受的编译时间内取得全局高质量结果。本文提出把这类流水线的编译分解为三个阶段:Transformation 改写程序,使其改用更充裕的流水线资源而避开稀缺资源;Synthesis 把复杂的事务型代码拆解为流水化计算单元的配置;Allocation 将程序的计算与内存映射到流水线硬件资源。三个阶段大量借助求解器引擎(ILP、SMT 与程序综合)来简化实现。作者实现了原型编译器 CaT,面向 Tofino 可编程交换流水线以及 RMT 流水线 Verilog 描述的周期精确模拟器 Menshen。实验表明,CaT 能编译现有编译器无法在流水线上运行的程序,编译速度更快,且生成代码占用的流水线资源更少。

问题
将高层程序编译到高速包处理流水线是一个组合优化问题,需要兼顾语义匹配与资源受限的装箱,而现有方法只处理其中个别方面,难以在合理编译时间内获得全局高质量结果。
方法
把该编译问题分解为变换、综合、分配三个阶段,并在各阶段大量复用 ILP、SMT 与程序综合等求解器引擎来降低实现难度。
评估
在 Tofino 可编程交换流水线与 RMT 流水线的周期精确模拟器 Menshen 上实现原型编译器 CaT,与已有编译器对比可编译程序的范围、编译速度以及生成代码的流水线资源占用。
原文摘要(Abstract)

Compiling high-level programs to high-speed packet-processing pipelines is a challenging combinatorial optimization problem. The compiler must configure the pipeline’s resources to match the semantics of the program’s high-level specification, while packing all of the program’s computation into the pipeline’s limited resources. State of the art approaches tackle individual aspects of this problem. Yet, they miss opportunities to produce globally high-quality outcomes within reasonable compilation times. We develop a framework to decompose the compilation problem for such pipelines into three phases—making extensive use of solver engines (e.g., ILP, SMT, and program synthesis) to simplify the development of these phases. Transformation rewrites programs to use more abundant pipeline resources, avoiding scarce ones. Synthesis breaks complex transactional code into configurations of pipelined compute units. Allocation maps the program’s compute and memory to the pipeline’s hardware resources. We prototype these ideas in a compiler, CaT, which targets (1) the Tofino programmable switch pipeline and (2) Menshen, a cycle-accurate simulator of a Verilog description of the RMT pipeline. CaT can handle programs that existing compilers cannot currently run on pipelines and generates code faster than existing compilers, where the generated code uses fewer pipeline resources.

链接与引用

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BibTeX
@inproceedings{paperbot10099,
  title = {CaT: A Solver-Aided Compiler for Packet-Processing Pipelines},
  author = {Xiangyu Gao and Divya Raghunathan and Ruijie Fang and Tao Wang and Xiaotong Zhu and Anirudh Sivaraman and Srinivas Narayana and Aarti Gupta},
  booktitle = {ASPLOS},
  year = {2023},
  doi = {10.1145/3582016.3582036}
}