一句话:提出 PipeSynth,在 RTL 实现完成之前自动合成处理器的微架构内存一致性公理,以支持早期形式验证。
形式验证有助于保证现代处理器的正确性,但其前提是拥有被验证处理器的形式化规约。目前这类微架构规约多由人工编写,过程繁琐且容易出错;硬件架构师与工程师通常又缺乏形式方法经验,使得编写规约更加困难。已有的微架构形式规约自动合成方法以处理器的 RTL 实现为输入,因此必须等到 RTL 实现完成之后才能使用,阻碍了形式验证在设计中前期的介入。PipeSynth 面向这一问题,自动合成刻画内存一致性的微架构公理,使形式验证不再被 RTL 实现的完成度所限制,从而有望在 RTL 之前发现设计缺陷,降低验证开销并缩短整体开发周期。摘要未给出具体合成算法与实验评估结果。
Formal verification can help ensure the correctness of today’s processors. However, such formal verification requires formal specifications of the processors being verified. Today, these specifications are mostly written by hand, which is tedious and error-prone. Furthermore, architects and hardware engineers generally do not have formal methods experience, making it even harder for them to write formal specifications. Existing methods for the automated synthesis of formal microarchitectural specifications utilise RTL implementations of processors for their synthesis, preventing their usage until RTL implementation of the processor has completed. This hampers the effectiveness of formal verification for processors, as catching design bugs pre-RTL can reduce verification overhead and overall development time.