一句话：提出 Manticore，用硬件加速与静态整体同步并行加速周期精确 RTL 仿真，以缩小与硬件三个数量级的速度差距。
摩尔定律与 Dennard 缩放终结使专用计算机体系结构和加速器重新受到关注，而这类硬件的验证与测试高度依赖寄存器传输级（RTL）设计的周期精确仿真。当前最快的软件 RTL 仿真器吞吐率仅为 1–1000 kHz，比硬件实际运行慢三个数量级以上，成为设计迭代与设计空间探索的瓶颈。针对该问题，Manticore 采用硬件加速与静态整体同步并行（BSP）来实现 RTL 仿真，目标是提高仿真速度与设计者生产力。摘要以仿真 kHz 吞吐率为核心衡量指标，并与现有最快软件 RTL 仿真器及硬件速度进行对比，但未报告 Manticore 的具体实验数据。
The demise of Moore's Law and Dennard Scaling has revived interest in specialized computer architectures and accelerators. Verification and testing of this hardware depend heavily upon cycle-accurate simulation of register-transfer-level (RTL) designs. The fastest software RTL simulators can simulate designs at 1--1000 kHz, i.e., more than three orders of magnitude slower than hardware. Improved simulators can increase designers' productivity by speeding design iterations and permitting more exhaustive exploration.
@inproceedings{paperbot10112,
title = {Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism},
author = {Mahyar Emami and Sahand Kashani and Keisuke Kamahori and Mohammad Sepehr Pourghannad and Ritik Raj and James R. Larus},
booktitle = {ASPLOS},
year = {2023},
doi = {10.1145/3623278.3624750}
}