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P2 Achieving Near-Zero Read Retry for 3D NAND Flash Memory

实现3D NAND闪存的近零读重试
ASPLOS Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 22024匹配度 0/10 · 该论文研究3D NAND闪存的读重试表与读电压优化,属于存储硬件/体系结构方向,与用户关注的程序语言、静态分析、LLM/Agent、浮点程序分析及贝叶斯程序分析均无直接关联。引用 16 inbox
Min Ye, Qiao Li, Yina Lv, Jie Zhang, Tianyu Ren, Daniel Wen, Tei-Wei Kuo, Chun Jason Xue
crossref: 2026-09-12dblp: 2026-09-12

AI 速览

一句话:提出针对每种闪存模型定制读重试表并动态选择与微调读电压的方法,使老化闪存读重试接近零。

随着3D NAND闪存因P/E循环老化,纠错所需的读重试次数不断增加,严重损害读性能。现有闪存芯片内置的预定义读重试表(RRT)未考虑读粒度和实际错误行为。该工作对多种真实闪存芯片进行表征,建立同一页各读电压最优读偏移之间的相关性模型;据此为每种闪存模型生成定制RRT,并设计动态读重试流程从表中选择合适读电压,再用邻近搜索微调读偏移。在真实芯片上的实验表明,该方法可将8K P/E循环、高保持时间数据的平均读重试次数降至0.003以下,接近零重试;而现有最佳方法在3K P/E循环后平均仍需超过3次读重试。

问题
老化3D NAND闪存纠错需频繁读重试,而内置预定义RRT未考虑读粒度与错误行为,导致读性能下降。
方法
表征真实闪存芯片并建模页内各读电压最优偏移的相关性,为每个闪存型号生成定制RRT,结合动态读电压选择与邻近搜索微调。
评估
在真实闪存芯片上实验,对比现有方法,测量不同P/E循环与保持时间下的平均读重试次数。
原文摘要(Abstract)

As the flash-based storage devices age with program/erase (P/E) cycles, they require an increasing number of read retries for error correction, which in turn deteriorates their read performance. The design of read-retry methods is critical to flash read performance. Current flash chips embed pre-defined read retry tables (RRT) for retry, but these tables fail to consider the read granularity and error behaviors. We characterize different types of real flash chips, based on which we further develop models for the correlation among the optimal read offsets of read voltages required for reading each page. By leveraging characterization observations and the models, we propose a methodology to generate a tailored RRT for each flash model. We introduce a dynamic read retry procedure to pick up proper read voltages from the table, followed by a proximity-search method for fine-tuning the read offsets. Experiments on real flash chips show that the proposed methodology can achieve near-zero retries. It reduces the average number of read retries to below 0.003 for data with high retention time at 8K P/E cycles, whereas the state-of-the-art approaches incur over 3 read retries on average once the flash is aged to 3K P/E cycles.

链接与引用

DOI 原文 · DBLP

BibTeX
@inproceedings{YeLLZRWKX24,
  title = {Achieving Near-Zero Read Retry for 3D NAND Flash Memory},
  author = {Min Ye and Qiao Li and Yina Lv and Jie Zhang and Tianyu Ren and Daniel Wen and Tei-Wei Kuo and Chun Jason Xue},
  booktitle = {ASPLOS},
  year = {2024},
  doi = {10.1145/3620665.3640372}
}