paperbot · PL 论文追踪

全部论文 待读 收藏

P2 A Fault-Tolerant Million Qubit-Scale Distributed Quantum Computer

容错百万量子比特级分布式量子计算机
ASPLOS Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 22024匹配度 1/10 · 论文聚焦分布式量子计算机的容错纠错软硬件协同设计,与用户关注静态分析、LLM/Agent、浮点程序分析和贝叶斯程序分析的核心方向无直接关联;仅“分布式与容错”标签在系统可靠性层面有表面联系。引用 32 inbox
Junpyo Kim, Dongmoon Min, Jungmin Cho, Hyeonseong Jeong, Ilkwon Byun, Junhyuk Choi, Juwon Hong, Jangwoo Kim
crossref: 2026-09-12dblp: 2026-09-12

AI 速览

一句话:提出多稀释制冷机分布式量子计算机的软硬件协同容错纠错机制,实现百万量子比特级容错计算。

百万量子比特级量子计算机需集成多个稀释制冷机(DR)中的量子处理器,但跨 DR 纠缠速度慢、错误率高且量子比特规模增大,使传统纠错因门操作数多和跨 DR 解码延迟大而失效。本文提出面向多 DR 分布式量子计算机的容错错误处理机制,通过软硬件协同设计实现:低开销多 DR 错误症状测量(ESM)序列以减少门操作数和错误率,以及可扩展多 DR 错误解码单元(EDU)架构以提升解码速度与精度。相比基线,ESM 延迟、ESM 错误、EDU 延迟和 EDU 精度分别提升 3.7 倍、2.4 倍、685 倍和 6.1×10^10 倍;在电压缩放 CMOS 与成熟 ERSFQ 技术假设下,构建了容错百万量子比特级量子计算机。

问题
多 DR 大规模量子计算机中,缓慢且易错的跨 DR 纠缠及量子比特规模增长使基线纠错机制因门操作数和解码延迟增加而失效。
方法
采用软硬件协同设计:低开销多 DR ESM 序列降低门操作与错误率,可扩展多 DR EDU 架构提升解码速度与精度。
评估
在假设的电压缩放 CMOS 与成熟 ERSFQ 工艺下,量化相比基线的 ESM 延迟、ESM 错误、EDU 延迟与 EDU 精度改进,并展示容错百万量子比特级构建。
原文摘要(Abstract)

A million qubit-scale quantum computer is essential to realize the quantum supremacy. Modern large-scale quantum computers integrate multiple quantum computers located in dilution refrigerators (DR) to overcome each DR's unscaling cooling budget. However, a large-scale multi-DR quantum computer introduces its unique challenges (i.e., slow and erroneous inter-DR entanglement, increased qubit scale), and they make the baseline error handling mechanism ineffective by increasing the number of gate operations and the inter-DR communication latency to decode and correct errors. Without resolving these challenges, it is impossible to realize a fault-tolerant large-scale multi-DR quantum computer. In this paper, we propose a million qubit-scale distributed quantum computer which uses a novel error handling mechanism enabling fault-tolerant multi-DR quantum computing. First, we apply a low-overhead multi-DR error syndrome measurement (ESM) sequence to reduce both the number of gate operations and the error rate. Second, we apply a scalable multi-DR error decoding unit (EDU) architecture to maximize both the decoding speed and accuracy. Our multi-DR error handling SW-HW co-design improves the ESM latency, ESM errors, EDU latency, and EDU accuracy by 3.7 times, 2.4 times, 685 times, and 6.1 · 1010 times, respectively. With our scheme applied to assumed voltage-scaled CMOS and mature ERSFQ technologies, we successfully build a fault-tolerant million qubit-scale quantum computer.

链接与引用

DOI 原文 · DBLP

BibTeX
@inproceedings{KimMCJBCHK24,
  title = {A Fault-Tolerant Million Qubit-Scale Distributed Quantum Computer},
  author = {Junpyo Kim and Dongmoon Min and Jungmin Cho and Hyeonseong Jeong and Ilkwon Byun and Junhyuk Choi and Juwon Hong and Jangwoo Kim},
  booktitle = {ASPLOS},
  year = {2024},
  doi = {10.1145/3620665.3640388}
}