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P2 CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators

CIM-MLC:面向存内计算加速器的多级编译栈
ASPLOS Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 22024匹配度 2/10 · 论文主题是面向存内计算加速器的多级编译栈与映射调度,属于体系结构/编译器优化,与用户核心关注的静态分析、LLM/Agent 程序分析、浮点程序分析、贝叶斯程序分析均无直接交集;仅“编译与代码生成”标签存在较弱的领域邻近性。引用 13 inbox
Songyun Qu, Shixin Zhao, Bing Li, Yintao He, Xuyi Cai, Lei Zhang, Ying Wang
crossref: 2026-09-12dblp: 2026-09-12arxiv: 2026-09-12

AI 速览

一句话:提出通用多级编译框架 CIM-MLC,用统一硬件抽象支持多种存内计算架构并优化映射调度。

存内计算(CIM)处理器在性能上优于传统架构,但其器件精度、crossbar 尺寸与数量等差异巨大。现有开源编译栈缺乏相应体系结构支持,设计者只能手工部署或为固定架构定制编译器,难以适配不同计算粒度。本文提出 CIM-MLC,一个面向通用 CIM 架构的多级编译框架。它首先建立统一的 CIM 硬件与计算模式抽象,以表示不同器件、架构和编程接口的加速器;在此基础上,CIM-MLC 可在 CIM 的多个体系结构层级上探索映射与调度策略,形成可处理且有效的设计空间,从而改进调度和指令生成。实验表明,相比已有面向 CIM 的编译工作,CIM-MLC 平均取得 3.2 倍推理加速。

问题
现有编译栈缺乏对 CIM 架构细节与实现多样性的支持,且已有工作多绑定固定 CIM 架构、仅处理有限算子调度,难以充分发挥不同 CIM 加速器的优势。
方法
建立通用 CIM 硬件与计算模式抽象,并据此构建多级编译框架,在多个体系结构层级上联合探索映射与调度策略以生成调度和指令。
评估
在多种 CIM 加速器上编译推理任务,与已有面向 CIM 的编译工作对比,平均取得 3.2 倍推理加速。
原文摘要(Abstract)

In recent years, various computing-in-memory (CIM) processors have been presented, showing superior performance over traditional architectures. To unleash the potential of various CIM architectures, such as device precision, crossbar size, and crossbar number, it is necessary to develop compilation tools that are fully aware of the CIM architectural details and implementation diversity. However, due to the lack of architectural support in current popular open-source compiling stacks such as TVM, existing CIM designs either manually deploy networks or build their own compilers, which is time-consuming and labor-intensive. Although some works expose the specific CIM device programming interfaces to compilers, they are often bound to a fixed CIM architecture, lacking the flexibility to support the CIM architectures with different computing granularity. On the other hand, existing compilation works usually consider the scheduling of limited operation types (such as crossbar-bound matrix-vector multiplication). Unlike conventional processors, CIM accelerators are featured by their diverse architecture, circuit, and device, which cannot be simply abstracted by a single level if we seek to fully explore the advantages brought by CIM. Therefore, we propose CIM-MLC, a universal multi-level compilation framework for general CIM architectures. In this work, we first establish a general hardware abstraction for CIM architectures and computing modes to represent various CIM accelerators. Based on the proposed abstraction, CIM-MLC can compile tasks onto a wide range of CIM accelerators having different devices, architectures, and programming interfaces. More importantly, compared with existing compilation work, CIM-MLC can explore the mapping and scheduling strategies across multiple architectural tiers in CIM, which form a tractable yet effective design space, to achieve better scheduling and instruction generation results. Experimental results show that CIM-MLC achieves 3.2× inference speedup on average compared to prior CIM-oriented compilation work.

链接与引用

DOI 原文 · arXiv · PDF(开放获取) · DBLP

BibTeX
@inproceedings{QuZLHCZW24,
  title = {CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators},
  author = {Songyun Qu and Shixin Zhao and Bing Li and Yintao He and Xuyi Cai and Lei Zhang and Ying Wang},
  booktitle = {ASPLOS},
  year = {2024},
  doi = {10.1145/3620665.3640359}
}