一句话：提出支持用户控制缓存写回的微架构扩展与 Skip It 机制，在 RISC-V BOOM 上减少冗余写回。
显式管理缓存中数据的存在对于现代系统的正确性和性能至关重要，但此类操作往往带来显著性能开销，且因硬件实现专有、缺乏文档，优化研究多受限于缓慢的简化软件模拟。本文设计微架构扩展，支持两类用户控制的缓存写回主存操作，并提出 Skip It 机制以大幅减少冗余写回。作者在开源 BOOM 乱序 RISC-V CPU 上实现这些设计。硬件性能约为 100 周期，优于商用服务器级平台的类似操作；Skip It 在避免不必要写回方面达到或优于现有最先进软件技术。
Mechanisms to explicitly manage the presence of data in caches are fundamental for the correctness and performance of modern systems. These operations, while critical, often incur significant performance penalties even when carefully used. Moreover, these mechanisms are implemented in proprietary and often undocumented hardware, so research into optimizations and novel designs is mostly limited to slow, simplified software simulations. In this paper, we design microarchitectural extensions to support two types of user-controlled cache writebacks to main memory. Furthermore, we propose Skip It, a mechanism built on top of our extensions that substantially reduces redundant writebacks. We implemented these designs on the open-source BOOM out-of-order RISC-V CPU. The performance in hardware is ≈ 100 cycles which favorably compares to similar operations in commercially available server-class platforms. In addition, Skip It performs as well as or better than state-of-the-art software techniques for avoiding unnecessary writebacks.