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P2 Marple: Scalable Spike Sorting for Untethered Brain-Machine Interfacing

Marple:面向无束缚脑机接口的可扩展峰电位分类
ASPLOS Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 22024匹配度 0/10 · 论文研究神经信号spike sorting的专用硬件流水线与模板存储优化,属于计算神经科学/体系结构方向;虽提到用ML替代模板匹配,但未涉及静态分析、LLM/Agent、浮点程序分析或贝叶斯程序分析。引用 7 inbox
Eugene Sha, Andy Liu, Kareem Ibrahim, Mostafa Mahmoud, Christina Giannoula, Ameer Abdelhadi, Andreas Moshovos
crossref: 2026-09-12dblp: 2026-09-12

AI 速览

一句话:提出可扩展硬件流水线 Marple,通过将模板存储降低 8–11 倍,在 7nm 下以 79mW 支持 10K 通道实时 spike sorting。

无束缚脑机接口中的 spike sorting 需要在大规模通道下实时运行。传统软件方法精度高,但依赖高功耗 GPU 且只能事后处理;硬件方法虽可便携,却因简化机制损失精度,通常仅支持最多 128 路输入。该工作分析现代软件 spike sorter 的计算与内存需求,发现模板存储是主要瓶颈。作者提出 Marple:一个可扩展硬件流水线,使用新机制将模板存储降低 8–11 倍;前端固定功能模块将输入流过滤为感兴趣区域,后端以灵活向量运算完成神经元识别。作者还首次用机器学习替代模板匹配阶段。在 7nm 工艺、10K 通道峰值活动下,预计功耗仅 79mW。

问题
在无束缚脑机接口中,传统 spike sorting 软件精度高但需事后处理和高功耗 GPU;硬件方案则受限于精度与最多 128 路输入。
方法
分析现代软件 spike sorter 的计算/存储瓶颈(尤其模板存储),设计可扩展硬件流水线 Marple:固定功能前端过滤 + 向量后端识别,并用新机制压缩模板存储 8–11 倍;还首次用 ML 替代模板匹配阶段。
评估
通过架构分析与投影评估,在 7nm 工艺、10K 通道峰值活动下预计功耗 79mW。
原文摘要(Abstract)

Spike sorting is the process of parsing electrophysiological signals from neurons to identify if, when, and which particular neurons fire. Spike sorting is a particularly difficult task in computational neuroscience due to the growing scale of recording technologies and complexity in traditional spike sorting algorithms. Previous spike sorters can be divided into software-based and hardware-based solutions. Software solutions are highly accurate but operate on recordings after-the-fact, and often require utilization of high-power GPUs to process in a timely fashion, and they cannot be used in portable applications. Hardware solutions suffer in terms of accuracy due to the simplification of mechanisms for implementation's sake and process only up to 128 inputs. This work answers the question: "How much computation power and memory storage is needed to sort spikes from 1000s of channels to keep up with advances in probe technology?" We analyze the computational and memory requirements for modern software spike sorters to identify their potential bottlenecks - namely in the template memory storage. We architect Marple, a highly optimized hardware pipeline for spike sorting which incorporates a novel mechanism to reduce the template memory storage from 8 - 11x. Marple is scalable, uses a flexible vector-based back-end to perform neuron identification, and a fixed-function front-end to filter the incoming streams into areas of interest. The implementation is projected to use just 79mW in 7nm, when spike sorting 10K channels at peak activity. We further demonstrate, for the first time, a machine learning replacement for the template matching stage.

链接与引用

DOI 原文 · DBLP

BibTeX
@inproceedings{ShaLIMGAM24,
  title = {Marple: Scalable Spike Sorting for Untethered Brain-Machine Interfacing},
  author = {Eugene Sha and Andy Liu and Kareem Ibrahim and Mostafa Mahmoud and Christina Giannoula and Ameer Abdelhadi and Andreas Moshovos},
  booktitle = {ASPLOS},
  year = {2024},
  doi = {10.1145/3620665.3640357}
}