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P2 ACES: Accelerating Sparse Matrix Multiplication with Adaptive Execution Flow and Concurrency-Aware Cache Optimizations

ACES:利用自适应执行流和并发感知缓存优化加速稀疏矩阵乘法
ASPLOS Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 32024匹配度 1/10 · 该论文研究 SpMM 专用加速器与缓存优化,属于计算机体系结构与高性能计算方向;与用户关注的静态分析、LLM/Agentic 程序分析、浮点程序分析及贝叶斯程序分析均无直接交集。虽然 SpMM 常用于机器学习,但本文不涉及 PL/AI 交叉或程序分析。引用 12 inbox
Xiaoyang Lu, Boyu Long, Xiaoming Chen, Yinhe Han, Xian-He Sun
crossref: 2026-09-12dblp: 2026-09-12

AI 速览

一句话:提出 SpMM 加速器 ACES,通过自适应执行流与并发感知全局缓存优化实现 2.1 倍加速。

稀疏矩阵乘法(SpMM)广泛用于科学与机器学习,但存在大量不规则内存访问,对传统缓存架构构成挑战。已有 SpMM 加速器难以适应多样稀疏模式、充分利用并行性并优化缓存性能。为此,本文提出 ACES 加速器:其自适应执行流可根据稀疏模式动态调整,在并行计算效率与数据复用之间取得平衡;在全局缓存中引入局部性与并发性协同优化,采用并发感知缓存替换策略并集成非阻塞缓冲区以提升并发、减少停顿;硬件架构统一支持上述机制与细粒度并行。评估显示 ACES 相较现有方案取得 2.1 倍加速,显著推进了 SpMM 加速。

问题
SpMM 的不规则内存访问使传统缓存架构难以高效支撑;现有加速器在适应多样稀疏模式、挖掘并行性和优化缓存方面仍有不足。
方法
提出 ACES 加速器,包含可动态适配稀疏模式的自适应执行流,以及全局缓存中的局部性-并发性协同优化、并发感知替换策略和非阻塞缓冲。
评估
通过性能评估与现有方案对比,ACES 取得 2.1 倍加速,验证了其在 SpMM 加速上的有效性。
原文摘要(Abstract)

Sparse matrix-matrix multiplication (SpMM) is a critical computational kernel in numerous scientific and machine learning applications. SpMM involves massive irregular memory accesses and poses great challenges to conventional cache-based computer architectures. Recently dedicated SpMM accelerators have been proposed to enhance SpMM performance. However, current SpMM accelerators still face challenges in adapting to varied sparse patterns, fully exploiting inherent parallelism, and optimizing cache performance. To address these issues, we introduce ACES, a novel SpMM accelerator in this study. First, ACES features an adaptive execution flow that dynamically adjusts to diverse sparse patterns. The adaptive execution flow balances parallel computing efficiency and data reuse. Second, ACES incorporates locality-concurrency co-optimizations within the global cache. ACES utilizes a concurrency-aware cache management policy, which considers data locality and concurrency for optimal replacement decisions. Additionally, the integration of a non-blocking buffer with the global cache enhances concurrency and reduces computational stalls. Third, the hardware architecture of ACES is designed to integrate all innovations. The architecture ensures efficient support across the adaptive execution flow, advanced cache optimizations, and fine-grained parallel processing. Our performance evaluation demonstrates that ACES significantly outperforms existing solutions, providing a 2.1× speedup and marking a substantial advancement in SpMM acceleration.

链接与引用

DOI 原文 · PDF(开放获取) · DBLP

BibTeX
@inproceedings{LuL00S24,
  title = {ACES: Accelerating Sparse Matrix Multiplication with Adaptive Execution Flow and Concurrency-Aware Cache Optimizations},
  author = {Xiaoyang Lu and Boyu Long and Xiaoming Chen and Yinhe Han and Xian-He Sun},
  booktitle = {ASPLOS},
  year = {2024},
  doi = {10.1145/3620666.3651381}
}