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P2 AERO: Adaptive Erase Operation for Improving Lifetime and Performance of Modern NAND Flash-Based SSDs

AERO:面向现代 NAND Flash SSD 寿命与性能提升的自适应擦除操作
ASPLOS Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 32024匹配度 0/10 · 该论文研究 NAND 闪存擦除时延优化与 SSD 寿命/性能,属于存储体系结构方向,与用户关注的程序分析、LLM/Agent、浮点程序分析和贝叶斯程序分析均无直接关联。引用 20 inbox
Sungjun Cho, Beomjun Kim, Hyunuk Cho, Gyeongseob Seo, Onur Mutlu, Myungsuk Kim, Jisung Park
crossref: 2026-09-12dblp: 2026-09-12arxiv: 2026-09-12

AI 速览

一句话:提出 AERO,依据擦除失败位数动态预测近最优擦除时延,延长 SSD 寿命并降低读尾延迟。

NAND Flash 擦除操作需施加高压并持续较长时间,会损伤单元耐久性,并可能延迟用户 I/O 请求。现有工作多采用覆盖最差工况的固定擦除时延,未充分探索擦除时延的最优设置。本文提出 AERO:一种根据目标单元当前擦除特性,将擦除时延动态调整为恰好足够可靠擦除的自适应方案。AERO 利用擦除过程中的失败位数预测近最优擦除时延,并通过先短时擦除获取必要失败位数、利用现代 SSD 的可靠性余量安全地激进降低时延。作者在 160 片真实 3D NAND 芯片上验证了可行性与可靠性,显示在不修改现有芯片的情况下将 SSD 寿命较传统方案提升 43%。基于 11 个真实负载的系统级评估表明,启用 AERO 的 SSD 相比当前最优技术平均降低读尾延迟 34%。

问题
NAND Flash 擦除操作需要高压和长时间,会降低单元耐久性并可能延迟用户 I/O;现有方案通常使用覆盖最差工况的固定擦除时延,未研究如何设置擦除时延以充分发挥 NAND Flash 潜力。
方法
AERO 根据目标单元当前擦除特性动态调整擦除时延,使其恰好足够可靠擦除目标单元;它通过擦除中的失败位数预测近最优时延,并采用先短时擦除以获取失败位数、利用现代 SSD 可靠性余量安全降低时延两项优化。
评估
作者使用 160 片真实 3D NAND Flash 芯片验证 AERO 的可行性与可靠性,并基于 11 个真实工作负载进行系统级评估。结果表明,AERO 在不改变现有 NAND 芯片的情况下将 SSD 寿命较传统方案提升 43%,且相较当前最优技术平均降低读尾延迟 34%。
原文摘要(Abstract)

This work investigates a new erase scheme in NAND flash memory to improve the lifetime and performance of modern solid-state drives (SSDs). In NAND flash memory, an erase operation applies a high voltage (e.g., > 20 V) to flash cells for a long time (e.g., > 3.5 ms), which degrades cell endurance and potentially delays user I/O requests. While a large body of prior work has proposed various techniques to mitigate the negative impact of erase operations, no work has yet investigated how erase latency should be set to fully exploit the potential of NAND flash memory; most existing techniques use a fixed latency for every erase operation which is set to cover the worst-case operating conditions. To address this, we propose Aero (Adaptive ERase Operation), a new erase scheme that dynamically adjusts erase latency to be just long enough for reliably erasing target cells, depending on the cells' current erase characteristics. Aero accurately predicts such near-optimal erase latency based on the number of fail bits during an erase operation. To maximize its benefits, we further optimize Aero in two aspects. First, at the beginning of an erase operation, Aero attempts to erase the cells for a short time (e.g., 1 ms), which enables Aero to always obtain the number of fail bits necessary to accurately predict the near-optimal erase latency. Second, Aero aggressively yet safely reduces erase latency by leveraging a large reliability margin present in modern SSDs. We demonstrate the feasibility and reliability of Aero using 160 real 3D NAND flash chips, showing that it enhances SSD lifetime over the conventional erase scheme by 43% without change to existing NAND flash chips. Our system-level evaluation using eleven real-world workloads shows that an AERO-enabled SSD reduces read tail latency by 34% on average over a state-of-the-art technique.

链接与引用

DOI 原文 · arXiv · PDF(开放获取) · DBLP

BibTeX
@inproceedings{abs-2404-10355,
  title = {AERO: Adaptive Erase Operation for Improving Lifetime and Performance of Modern NAND Flash-Based SSDs},
  author = {Sungjun Cho and Beomjun Kim and Hyunuk Cho and Gyeongseob Seo and Onur Mutlu and Myungsuk Kim and Jisung Park},
  booktitle = {ASPLOS},
  year = {2024},
  doi = {10.1145/3620666.3651341}
}