一句话：提出 CoreDSL 描述语言与 Longnail 高层次综合工具，实现 RISC-V 定制指令扩展的端到端生成与自动集成。
在 RISC-V 生态中，定制指令集架构扩展（ISAX）是加速嵌入式负载的高能效途径，但针对特定应用探索基础核与 ISAX 组合需要自动化及跨微架构可移植性，现有方法难以满足。为此，本文提出端到端的 ISAX 规约、生成与集成流程：规约语言 CoreDSL 是一种简洁易学、开源的行为级架构描述语言；硬件生成由领域特定高层次综合工具 Longnail 完成，它将 CoreDSL 规约编译为兼容 SCAIE-V 扩展接口的硬件模块，并借助该接口自动集成到宿主核中。评估方面，作者生成混合了多周期计算、内存访问、分支指令、自定义寄存器与解耦执行等特性的 ISAX，集成到四种嵌入式核，并在 22nm ASIC 工艺下评估结果质量。
In the RISC-V ecosystem, custom instruction set architecture extensions (ISAX) are an energy-efficient and cost-effective way to accelerate modern embedded workloads. However, exploring different combinations of base cores and ISAXes for a specific application requires automation and a level of portability across microarchitectures that is not provided by existing approaches. To that end, we present an end-to-end flow for ISAX specification, generation, and integration into a number of host cores having a range of different microarchitectures. For ISAX specification, we propose CoreDSL, a novel behavioral architecture description language that is concise, easy to learn, and open source. Hardware generation is handled by Longnail, a domain-specific high-level synthesis tool that compiles CoreDSL specifications into hardware modules compatible with the recently introduced SCAIE-V extension interface, which we rely on for automatic integration into the host cores. We demonstrate our tooling by generating ISAXes using a mix of features, including complex multi-cycle computations, memory accesses, branch instructions, custom registers, and decoupled execution across four embedded cores and evaluate the quality of results on a 22nm ASIC process.
@inproceedings{OppermannDMMJ024,
title = {Longnail: High-Level Synthesis of Portable Custom Instruction Set Extensions for RISC-V Processors from Descriptions in the Open-Source CoreDSL Language},
author = {Julian Oppermann and Brindusa Mihaela Damian-Kosterhon and Florian Meisel and Tammo Mürmann and Eyck Jentzsch and Andreas Koch},
booktitle = {ASPLOS},
year = {2024},
doi = {10.1145/3620666.3651375}
}