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P2 TAROT: A CXL SmartNIC-Based Defense Against Multi-bit Errors by Row-Hammer Attacks

TAROT:一种基于 CXL SmartNIC 的 Row Hammer 攻击多比特错误防御方案
ASPLOS Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 32024匹配度 0/10 · 该论文研究 Row Hammer 攻击下的 DRAM 多比特错误防御,属于硬件安全与体系结构方向,未涉及程序分析、静态分析、形式化验证、浮点程序分析、贝叶斯程序分析,也未涉及 LLM/Agent,与用户画像的核心研究方向完全无关。引用 14 inbox
Chihun Song, Michael Jaemin Kim, Tianchen Wang, Houxiang Ji, Jinghan Huang, Ipoom Jeong, Jaehyun Park, Hwayong Nam, Minbok Wi, Jung Ho Ahn, Nam Sung Kim
crossref: 2026-09-12dblp: 2026-09-12

AI 速览

一句话:通过 3 周 DRAM 实验发现 Row Hammer 多比特错误仅集中于少量地址,提出 H-TAROT 软件防御与 SmartNIC 卸载的 S-TAROT,性能开销极低。

Row Hammer(RH)攻击可在现代 DRAM 中引发多比特不可纠正错误(UE),即使有 ECC 也会导致系统崩溃。本文首先对现代 DRAM 模块进行为期 3 周的 RH 实验,发现 RH 引发的 UE 仅出现在少数特定地址(RH-UE-vulnerable addresses),且占比很小。基于此,作者提出两种防御方案:H-TAROT 是运行在宿主 CPU 上的软件方案,在系统启动时获取易受攻击地址,并周期性地在这些地址发生 UE 前访问它们;由于只访问少量地址,其对吞吐型应用影响小,但会显著增加延迟敏感型应用尾延迟。为降低开销,S-TAROT 将 H-TAROT 从宿主 CPU 卸载到 SmartNIC CPU。评估显示,H-TAROT 使 SPECrate 2017 执行时间增加 1.5%,Redis 尾延迟增加 28.2%;S-TAROT 则将二者分别降至 0.1% 和 1.0%。

问题
Row Hammer 攻击可在 DRAM 中引发多比特不可纠正错误(UE),仅靠商用 CPU 的 ECC 无法纠正,进而导致系统崩溃。
方法
对现代 DRAM 模块进行 3 周 RH 实验以定位 RH-UE-vulnerable addresses,并据此提出 H-TAROT 软件方案及将其卸载到 SmartNIC CPU 的 S-TAROT 方案。
评估
在 SPECrate 2017 与 Redis 上测量执行时间和尾延迟,对比 H-TAROT 与 S-TAROT 的性能开销。
原文摘要(Abstract)

Row Hammer (RH) has been demonstrated as a security vulnerability in modern systems. Although commodity CPUs can handle RH-induced single-bit errors in DRAM through ECC, RH can still give rise to multi-bit uncorrectable errors (UEs) and crash the systems. Meanwhile, recent work has indicated that the DRAM cells vulnerable to RH are determined by manufacturing imperfections and resulting defects. Taking one step further from the recent work, we first conduct RH experiments on contemporary DRAM modules for 3 weeks. This demonstrates that RH-induced UEs occur only at specific DRAM addresses (RH-UE-vulnerable addresses) and the percentage of such addresses is small in these DRAM modules. Second, to protect the systems from RH-induced UEs, we propose two RH defense solutions: H- and S-TAROT (TArgeted ROw-Hammer Therapy). H-TAROT is a software-based solution running on the host CPU. It obtains RH-UE-vulnerable addresses during the system boot and then periodically accesses such addresses before UEs may occur. Since it accesses only a small percentage of addresses, it does not incur a notable performance penalty for throughput applications (e.g., a 1.5% increase in execution time of the SPECrate 2017 benchmark suite running on a system even with 128GB of DRAM). Yet, it imposes a significant performance penalty on latency-sensitive applications (e.g., a 28.2% increase in tail latency of Redis). To minimize the performance penalty, for a system with a SmartNIC (SNIC), S-TAROT offloads H-TAROT from the host CPU to the SNIC CPU. Our experiment shows that S-TAROT increases the execution time and tail latency of the SPECrate 2017 benchmark suite and Redis by only 0.1% and 1.0%, respectively.

链接与引用

DOI 原文 · DBLP

BibTeX
@inproceedings{SongKWJHJ0NWAK24,
  title = {TAROT: A CXL SmartNIC-Based Defense Against Multi-bit Errors by Row-Hammer Attacks},
  author = {Chihun Song and Michael Jaemin Kim and Tianchen Wang and Houxiang Ji and Jinghan Huang and Ipoom Jeong and Jaehyun Park and Hwayong Nam and Minbok Wi and Jung Ho Ahn and Nam Sung Kim},
  booktitle = {ASPLOS},
  year = {2024},
  doi = {10.1145/3620666.3651325}
}