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P2 TAPA-CS: Enabling Scalable Accelerator Design on Distributed HBM-FPGAs

TAPA-CS:在分布式 HBM-FPGA 上实现可扩展加速器设计
ASPLOS Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 32024匹配度 1/10 · 该论文研究 FPGA 集群上的任务并行数据流编译与加速器设计,属于编译/体系结构方向,但未涉及用户画像中的静态分析、LLM/Agent、浮点程序分析或贝叶斯程序分析等核心问题。引用 6 inbox
Neha Prakriya, Yuze Chi, Suhail Basalama, Linghao Song, Jason Cong
crossref: 2026-09-12dblp: 2026-09-12arxiv: 2026-09-12

AI 速览

一句话:提出任务并行的数据流编程框架 TAPA-CS,可自动划分并跨 FPGA 集群编译大规模设计,同时保证高频与高吞吐。

针对云规模多 die FPGA 缺乏高效编程工具的问题,本文提出 TAPA-CS:一个任务并行的数据流编程框架,可自动将大规模设计划分并编译到 FPGA 集群。它开源并让用户利用近乎“无限”的加速器资源、HBM 与片上内存;能自动划分设计以实现拥塞控制、资源均衡及通信计算重叠;并将粗粒度布局规划与 FPGA 间/内互连流水化结合以保证高频。实验在 100Gbps 以太网连接的多 FPGA 测试床上评估脉动阵列 CNN、PageRank、模板计算与 KNN 等设计。相比 Vitis HLS 单 FPGA 基线,2、3、4 FPGA 设计平均加速 2.1×、3.2×、4.4×,频率提升 11%–116%。

问题
云规模、网络连接的多 die FPGA 缺乏可扩展的编程工具与抽象,难以生成高频高吞吐加速器。
方法
提出任务并行数据流框架 TAPA-CS,自动划分设计到 FPGA 集群,结合拥塞控制、资源均衡、通信计算重叠与粗/细粒度流水化布局。
评估
在 100Gbps 以太网连接的多 FPGA 测试床上评估 2/3/4 FPGA 设计(CNN、PageRank、模板计算、KNN),与 Vitis HLS 单 FPGA 基线比较加速比与频率提升。
原文摘要(Abstract)

Despite the increasing adoption of FPGAs in compute clouds, there remains a significant gap in programming tools and abstractions which can leverage network-connected, cloud-scale, multi-die FPGAs to generate accelerators with high frequency and throughput. We propose TAPA-CS, a task-parallel dataflow programming framework which automatically partitions and compiles a large design across a cluster of FPGAs while achieving high frequency and throughput. TAPA-CS has three main contributions. First, it is an open-source framework which allows users to leverage virtually "unlimited" accelerator fabric, high-bandwidth memory (HBM), and on-chip memory. Second, given as input a large design, TAPA-CS automatically partitions the design to map to multiple FPGAs, while ensuring congestion control, resource balancing, and overlapping of communication and computation. Third, TAPA-CS couples coarse-grained floor-planning with interconnect pipelining at the inter- and intra-FPGA levels to ensure high frequency. FPGAs in our multi-FPGA testbed communicate through a high-speed 100Gbps Ethernet infrastructure. We have evaluated the performance of TAPA-CS on designs, including systolic-array based CNNs, graph processing workloads such as page rank, stencil applications, and KNN. On average, the 2-, 3-, and 4-FPGA designs are 2.1×, 3.2×, and 4.4× faster than the single FPGA baselines generated through Vitis HLS. TAPA-CS also achieves a frequency improvement between 11%-116% compared with Vitis HLS.

链接与引用

DOI 原文 · arXiv · PDF(开放获取) · DBLP

BibTeX
@inproceedings{abs-2311-10189,
  title = {TAPA-CS: Enabling Scalable Accelerator Design on Distributed HBM-FPGAs},
  author = {Neha Prakriya and Yuze Chi and Suhail Basalama and Linghao Song and Jason Cong},
  booktitle = {ASPLOS},
  year = {2024},
  doi = {10.1145/3620666.3651347}
}