一句话：提出控制逻辑综合技术，从数据通路草图与架构规约自动合成控制逻辑，填补设计空洞。
面向 SoC 设计，架构规约、微架构数据通路与控制逻辑之间的复杂交互使设计难以兼顾敏捷性与正确性。本文提出“控制逻辑综合”技术：设计者只需给出数据通路草图，将控制逻辑留作空洞，再以架构规约为指导，将程序合成技术适配到硬件领域，自动生成正确的控制逻辑并填满空洞，从而完成设计。作者在状态机与指令译码器两类控制逻辑、以及嵌入式 RISC-V 核与密码学加速器等架构上评估该技术，表明面向敏捷开发的 SoC 设计者无需手写控制逻辑即可迭代设计，同时仅需少量微架构信息便能获得形式化保证。
System-on-chip (SoC) design requires complex reasoning about the interactions between an architectural specification, the microarchitectural datapath (e.g., functional units), and the control logic (which coordinates the datapath) to facilitate the critical computing tasks on which we all depend. Hardware specialization is now the expectation rather than the exception, meaning we need new hardware design tools to bring ideas to reality with both agility and correctness. We introduce a new technique, "control logic synthesis", which automatically generates control logic given a datapath description and an architectural specification. This enables an entirely new hardware design process where the designer only needs to write a datapath sketch, leaving the control logic as "holes." Then, guided by an architectural specification, we adapt program synthesis techniques to automatically generate a correct hardware implementation of the control logic, filling the holes and completing the design. We evaluate control logic synthesis over two classes of control (state machines and instruction decoders) and different architectures (embedded-class RISC-V cores and hardware accelerators for cryptography). We demonstrate how agile-oriented SoC developers can iterate over designs without writing control logic by hand yet still retain formal assurances with only minimal microarchitectural information.
@inproceedings{SiscoAMAKDSHB24,
title = {Control Logic Synthesis: Drawing the Rest of the OWL},
author = {Zachary D. Sisco and Andrew David Alex and Zechen Ma and Yeganeh Aghamohammadi and Boming Kong and Benjamin Darnell and Timothy Sherwood and Ben Hardekopf and Jonathan Balkind},
booktitle = {ASPLOS},
year = {2024},
doi = {10.1145/3622781.3674170}
}