一句话：提出基于主机 CPU TEE enclave 保护并认证 FPGA bitstream 的实用 FPGA TEE 设计。
CPU-FPGA 异构架构在云环境中加速计算密集型任务日益流行，但处理敏感数据需要可信执行环境。本文分析了设计 FPGA TEE 的需求、在商用现成（COTS）云 FPGA 服务上部署现有方案的挑战，以及既有工作多聚焦独立 FPGA TEE 的局限。Salus 复用主机侧 CPU TEE 中的 enclave，并创新性地改造 COTS FPGA bitstream 工具，结合安全增强的 FPGA IP，对 FPGA 侧加载的 bitstream 进行保护与认证。该设计以较小改动实现可部署的 FPGA TEE，面向异构云平台提供实用方案。摘要未给出具体性能数据。
CPU-FPGA heterogeneous architectures have become increasingly popular in cloud environments for accelerating compute-intensive tasks. Ensuring the protection of sensitive data processed by these architectures requires the presence of a trusted execution environment (TEE). This work highlights the requirements for designing an FPGA TEE, the challenges faced in deploying existing solutions on commercial-off-the-shelf (COTS) cloud FPGA services, and the limitations of previous works that primarily focus on standalone FPGA TEEs. In response to these challenges, Salus introduces an innovative approach by leveraging an enclave running on the host with a TEE-enabled CPU. This approach aims to protect and attest the bitstream loaded on the FPGA side. By repurposing COTS FPGA bitstream utilities in a novel manner and adopting a proposed security-enhanced FPGA IP, Salus presents a practical design for an FPGA TEE, with minor efforts required.
@inproceedings{ZouLWSGLGN00024,
title = {Salus: A Practical Trusted Execution Environment for CPU-FPGA Heterogeneous Cloud Platforms},
author = {Yu Zou and Yiran Li and Sheng Wang and Le Su and Zhen Gu and Yanheng Lu and Yijin Guan and Dimin Niu and Mingyu Gao and Yuan Xie and Feifei Li},
booktitle = {ASPLOS},
year = {2024},
doi = {10.1145/3622781.3674169}
}