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P2 GUST: Graph Edge-Coloring Utilization for Accelerating Sparse Matrix Vector Multiplication

GUST:利用图边着色加速稀疏矩阵向量乘
ASPLOS Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 42024匹配度 1/10 · 该论文是面向 SpMV 的硬件/软件协同设计与边着色调度加速器,属于体系结构和高性能计算方向;它与用户关注的 PL 与 AI/LLM/Agent、静态分析、浮点程序分析或贝叶斯程序分析均无直接关联。引用 8 inbox
Armin Gerami, Bahar Asgari
crossref: 2026-09-12dblp: 2026-09-12arxiv: 2026-09-12

AI 速览

一句话:通过硬件上分离乘法器与加法器实现跨行列资源共享,并用边着色调度消除冲突,从而加速 SpMV。

稀疏矩阵向量乘(SpMV)广泛用于科学计算与机器学习,但稀疏性使通用处理器与既有领域专用架构都难以充分利用硬件资源。本文提出软硬件协同设计 GUST,其核心思路是在硬件层面将乘法器与加法器分离,使多行、多列之间能够共享算术资源,从而提升硬件利用率并缓解稀疏性带来的性能损失;资源共享会引发冲突,作者为此设计了专门的边着色调度算法加以解决。在真实数据集上与多种先前领域专用架构的比较显示,GUST 平均硬件利用率为 33.67%。长度 256 与长度 87 的 GUST 相对长度 256 的一维脉动阵列(1D)分别取得平均 411× 与 108× 的加速,能效提升 137× 与 148×。FPGA 综合表明长度 256 的 GUST 算术单元数与 1D 相同,长度 87 则显著更少;与当前最优的 FPGA SpMV 加速器 Serpens 相比,在 9 个矩阵中有 7 个执行时间更低、4 个能耗更低。

问题
稀疏数据使通用处理器与现有 SpMV 专用架构难以达到峰值性能,硬件资源利用率受稀疏性限制而偏低。
方法
提出软硬件协同设计 GUST,在硬件中分离乘法器与加法器以支持跨多行多列的资源共享,并用专门设计的图边着色调度算法避免共享导致的冲突。
评估
在真实数据集上与多种领域专用架构比较硬件利用率,测量 SpMV 执行时间与能耗并与一维脉动阵列和 Serpens 对比,同时通过 FPGA 综合评估资源消耗。
原文摘要(Abstract)

Sparse matrix-vector multiplication (SpMV) plays a vital role in various scientific and engineering fields, from scientific computing to machine learning. Traditional general-purpose processors often fall short of their peak performance with sparse data, leading to the development of domain-specific architectures to enhance SpMV. Yet, these specialized approaches, whether tailored explicitly for SpMV or adapted from matrix-matrix multiplication accelerators, still face challenges in fully utilizing hardware resources as a result of sparsity. To tackle this problem, we introduce GUST, a hardware/software co-design, the key insight of which lies in separating multipliers and adders in the hardware, thereby enabling resource sharing across multiple rows and columns, leading to efficient hardware utilization and ameliorating negative performance impacts from sparsity. Resource sharing, however, can lead to collisions, a problem we address through a specially devised edge-coloring scheduling algorithm. Our comparisons with various prior domain specific architectures using real-world datasets shows the effectiveness of GUST, with an average hardware utilization of 33.67%. We further evaluate GUST by comparing SpMV execution time and energy consumption of length-256 and -87 GUST with length-256 1-dimensional systolic array (1D), achieving an average speedup of 411× and 108×, and energy efficiency improvement of 137× and 148×, respectively. To asses the implementation aspect, we compare resource consumption of GUST with 1D as a baseline through FPGA synthesis. Length-256 GUST uses the same number of arithmetic units as length-256 1D, while length-87 GUST uses considerably less. We also compare GUST with Serpens, a state-of-the-art FPGA-based SpMV accelerator, with GUST achieving lower execution time on seven out of nine matrices and lower energy consumption on four.

链接与引用

DOI 原文 · arXiv · PDF(开放获取) · DBLP

BibTeX
@inproceedings{GeramiA24,
  title = {GUST: Graph Edge-Coloring Utilization for Accelerating Sparse Matrix Vector Multiplication},
  author = {Armin Gerami and Bahar Asgari},
  booktitle = {ASPLOS},
  year = {2024},
  doi = {10.1145/3622781.3674186}
}