一句话：提出集成于 RTL 仿真器的粗粒度电路去重，通过共享模块实例代码减少缓存占用，加速仿真并提升吞吐。
数字集成电路设计需要大量 RTL 仿真，工业界常并行运行，但不同仿真并行执行的影响尚未被充分探索；同时现代硬件中组件复制日益普遍，而电路去重潜力多被忽视。作者将共享末级缓存定位为 RTL 仿真吞吐的主要瓶颈，提出一种集成于 RTL 仿真器的粗粒度电路去重方法：识别电路中同一模块的多个实例，生成可应用于这些实例的共享代码，从而提高代码复用、降低缓存占用，并惠及缓存和分支预测器等处理器部件。实验表明，该方法在单次仿真中最高带来 1.95× 加速，并使整体 RTL 仿真吞吐最高提升 2.09×。
Designing a digital integrated circuit requires many register transfer level (RTL) simulations for design, debugging, and especially verification. To cope with the slow speed of RTL simulation, industry frequently uses private server farms to run many simulations in parallel. Surprisingly, the implications of parallel runs of different RTL simulations have not been extensively explored. Moreover, in modern digital hardware, there is a growing trend to replicate components to scale out. However, the potential for circuit deduplication has been mostly overlooked. In this work, we pinpoint the shared last-level cache as the primary bottleneck impacting the throughput of RTL simulation. To address this issue, we propose a coarse-grained circuit deduplication strategy integrated into an RTL simulator. Our method involves identifying multiple instances of a single module within a digital circuit and creating shared code that can be applied to all of these instances. Our approach reduces the cache footprint by increasing code reuse, which consequently benefits processor components such as caches and branch predictors. Our experiments demonstrate that deduplication can bring up to 1.95× speedup in a single simulation, and achieve up to 2.09× overall RTL simulation throughput.