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P2 Proactive Runtime Detection of Aging-Related Silent Data Corruptions: A Bottom-Up Approach

主动运行时检测老化相关的静默数据损坏:一种自底向上的方法
ASPLOS Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 42024匹配度 2/10 · 论文关注硬件老化导致的静默数据损坏,用形式验证生成运行时测试用例,目标在体系结构与硬件可靠性,而非用户核心的 PL/AI、Agentic 程序静态分析或浮点程序分析。虽然涉及形式验证和 FPU 测试,但 FPU 只是被测试的硬件单元,不是浮点程序分析,也没有 LLM/Agent 交叉。引用 6 inbox
Jiacheng Ma, Majd Ganaiem, Madeline Burbage, Theo Gregersen, Rachel McAmis, Freddy Gabbay, Baris Kasikci
crossref: 2026-09-12dblp: 2026-09-12

AI 速览

一句话:提出 Vega 工作流,利用老化建模与形式验证生成测试,在运行时低开销检测老化导致的静默数据损坏。

半导体工艺进步使晶体管老化逐渐降低门电路性能,并可能引发无日志、无异常的静默数据损坏(SDC),如指令误算、位翻转和缓存一致性破坏;设计阶段难以完全消除该问题。论文提出 Vega,一种自底向上的软件运行时检测工作流:先利用门级老化模型识别易受老化影响而失效的信号传播路径,再用形式验证生成短测试用例来激活这些路径并检测故障,最后通过直接融合或封装为库的方式将测试用例集成到用户应用中。作者在 RISC-V CPU 的 ALU 和 FPU 上评估,表明 Vega 生成的测试用例有效,集成后平均性能开销仅 0.8%。

问题
如何在软件运行时主动检测由晶体管老化引起的硬件静默数据损坏,而设计/制造阶段无法完全消除该问题。
方法
Vega 结合门级老化建模识别易失效信号路径,用形式验证生成短测试用例,并以直接融合或库调用方式集成到应用中。
评估
在 RISC-V CPU 的 ALU 和 FPU 上评估测试用例有效性及运行时开销,平均性能开销 0.8%。
原文摘要(Abstract)

Recent advancements in semiconductor process technologies have unveiled the susceptibility of hardware circuits to reliability issues, especially those related to transistor aging. Transistor aging gradually degrades gate performance, eventually causing hardware to behave incorrectly. Such misbehaving hardware can result in silent data corruptions (SDCs) in software---a type of failure that comes without logs or exceptions, but causes miscomputing instructions, bitflips, and broken cache coherency. Alas, while design efforts can be made to mitigate transistor aging, complete elimination of this problem during design and fabrication cannot be guaranteed. This emerging challenge calls for a mechanism that not only detects potentially aged hardware in the field, but also triggers software mitigations at application runtime. We propose Vega, a novel workflow that allows efficient detection of aging-related failures at software runtime. Vega leverages the well-studied gate-level modeling of aging effects to identify susceptible signal propagation paths that could fail due to transistor aging. It then utilizes formal verification techniques to generate short test cases that activate these paths and detect any failure within them. Vega integrates the test cases into a user application by directly fusing them together, or by packaging the test cases into a library that the application can invoke. We demonstrate our proposed techniques on the arithmetic logic unit and floating-point unit of a RISC-V CPU. We show that Vega generates effective test cases and integrates them into applications with an average of 0.8% performance overhead.

链接与引用

DOI 原文 · PDF(开放获取) · DBLP

BibTeX
@inproceedings{0001GBGMGK24,
  title = {Proactive Runtime Detection of Aging-Related Silent Data Corruptions: A Bottom-Up Approach},
  author = {Jiacheng Ma and Majd Ganaiem and Madeline Burbage and Theo Gregersen and Rachel McAmis and Freddy Gabbay and Baris Kasikci},
  booktitle = {ASPLOS},
  year = {2024},
  doi = {10.1145/3622781.3674182}
}