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P2 ARC: Warp-level Adaptive Atomic Reduction in GPUs to Accelerate Differentiable Rendering

ARC:GPU中Warp级自适应原子归约以加速可微分渲染
ASPLOS Proceedings of the 30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 12025匹配度 2/10 · 该论文属于GPU体系结构与可微分渲染性能优化,核心是warp级原子归约与原子计算分配,与用户关注的静态分析、LLM/Agent、浮点程序分析或贝叶斯程序分析均无直接关联。仅在广义机器学习系统性能优化层面有非常弱的交集,不涉及PL或形式化方法。引用 19 inbox
Sankeerth Durvasula, Adrian Zhao, Fan Chen, Ruofan Liang, Pawan Kumar Sanjaya, Yushi Guan, Christina Giannoula, Nandita Vijaykumar
crossref: 2026-09-12dblp: 2026-09-12

AI 速览

一句话:提出ARC,通过Warp级寄存器归约并分配核心与L2原子计算,加速可微分渲染的梯度更新。

可微分渲染将3D场景表示为可从2D图像训练得到的模型,但训练耗时很长。作者发现,梯度计算阶段的大量原子操作会压垮GPU L2缓存的原子单元,造成严重停顿。基于两个观察:多数Warp中所有线程原子更新同一内存位置;不同Warp产生的原子流量不同,论文提出ARC原语。ARC首先在GPU核心内利用寄存器进行Warp级归约,以利用Warp内原子更新的局部性;其次将原子计算在核心与L2原子单元之间分配,提高原子计算吞吐。作者给出硬件方案ARC-HW与纯软件方案ARC-SW。在广泛使用的可微分渲染负载上,ARC平均加速2.6倍,最高可达5.7倍。

问题
可微分渲染模型训练中,梯度计算产生的大量原子操作会压垮GPU L2原子单元,导致显著停顿。
方法
利用Warp内原子更新的局部性,在GPU核心内用寄存器进行Warp级归约,并在核心与L2原子单元之间分配原子计算;实现为硬件版ARC-HW和纯软件版ARC-SW。
评估
在广泛使用的可微分渲染负载上进行性能评估,ARC平均取得2.6倍加速,最高达到5.7倍。
原文摘要(Abstract)

Differentiable rendering is widely used in emerging applications that represent any 3D scene as a model trained using gradient descent from 2D images. Recent works (e.g., 3D Gaussian Splatting) use rasterization to enable rendering photo-realistic imagery at high speeds from these learned 3D models. These rasterization-based differentiable rendering methods have been demonstrated to be very promising, providing state-of-art quality for various important tasks. However, training a model to represent a scene is still time-consuming even on powerful GPUs. In this work, we observe that the gradient computation step during model training is a significant bottleneck due to the large number of atomic operations. These atomics overwhelm the atomic units in the L2 cache of GPUs, causing long stalls. To address this, we leverage the observations that during gradient computation: (1) for most warps, all threads atomically update the same memory locations; and (2) warps generate varying amount of atomic traffic. We propose ARC, a primitive that accelerates atomic operations based on two key ideas: First, we enable warp-level reduction at the GPU cores using registers to leverage the locality in intra-warp atomic updates. Second, we distribute atomic computation between the cores and the L2 atomic units to increase the throughput of atomic computation. We propose two implementations of ARC: ARC-HW, a hardware-based approach and ARC-SW, a software-only approach. We demonstrate significant speedups with ARC of 2.6× on average (up to 5.7×) for widely used differentiable rendering workloads.

链接与引用

DOI 原文 · DBLP

BibTeX
@inproceedings{DurvasulaZCLSGG25,
  title = {ARC: Warp-level Adaptive Atomic Reduction in GPUs to Accelerate Differentiable Rendering},
  author = {Sankeerth Durvasula and Adrian Zhao and Fan Chen and Ruofan Liang and Pawan Kumar Sanjaya and Yushi Guan and Christina Giannoula and Nandita Vijaykumar},
  booktitle = {ASPLOS},
  year = {2025},
  doi = {10.1145/3669940.3707238}
}