一句话：提出 STLB 与 L2 缓存协同的指令感知替换策略 iTP+xPTP，大幅缓解指令 TLB 缺失导致的流水线停顿。
现代服务器与数据中心应用不仅数据集庞大，指令足迹也很大，指令访问会频繁引发缓存与 TLB 缺失；其中指令 TLB 缺失尤为有害，因为它直接造成流水线停顿、显著降低性能。本文提出面向大指令足迹负载的末级 TLB（STLB）与 L2 缓存（L2C）协同替换策略。作者首先提出指令翻译优先（iTP），一种 STLB 替换策略，以增加数据页表遍历为代价最大化 STLB 中的指令命中；为补偿这一代价，又提出扩展页表优先（xPTP），一种新的 L2C 替换策略，通过有效减少数据页表遍历引发的 L2C 缺失来放大 iTP 的收益。二者组合为 iTP+xPTP，并配有自适应机制，可依据虚拟内存子系统承受的压力在 L2C 上于 xPTP 与 LRU 之间切换。在一组当代服务器负载上，该方案相对 STLB 与 L2C 均采用 LRU 的基线，单核几何平均性能提升 18.9%，SMT 共置场景下提升 11.4%，并优于当前最先进的 STLB 与缓存替换策略。
Modern server and data center applications are characterized not only by big datasets, but also by large instruction footprints that incur frequent cache and Translation Lookaside Buffer (TLB) misses due to instruction accesses. Instruction TLB misses are particularly problematic since they cause pipeline stalls that significantly harm performance. This paper proposes cooperative last-level TLB (STLB) and L2 cache (L2C) replacement policies targeting workloads with large instruction footprints. We propose the Instruction Translation Prioritization (iTP), an STLB replacement policy that maximizes the number of instruction hits in the STLB at the expense of increasing data page walks. To compensate for the increase of data page walks, we propose the extended Page Table Prioritization (xPTP), a new L2C replacement policy that amplifies the benefits of iTP by effectively reducing L2C misses due to data page walks. Our proposal, iTP+xPTP, combines iTP at STLB and xPTP at L2C. In addition, iTP+xPTP employs an adaptive mechanism that switches between xPTP and LRU policies at L2C based on the pressure placed on the virtual memory subsystem. Our proposal improves single-core geometric mean performance by 18.9% over a baseline that uses the LRU replacement policy at both STLB and L2C across a set of contemporary server workloads. Under SMT co-location, the corresponding performance uplift is 11.4%. Finally, we show that our proposal outperforms the state-of-the-art STLB and cache replacement policies.