一句话：提出 Plaid 架构与编译器，通过识别数据流图中的通信 motif 并集体执行与路由，对齐 CGRA 的计算与通信能力。
粗粒度可重构阵列（CGRA）是面向边缘设备的领域无关加速器，但其通信资源常相对于有限的计算能力过度供给，理论上的可编程性在实际中往往冗余。本文提出 Plaid，一种新的 CGRA 架构与编译器，旨在对齐计算与通信能力，同时保持通用性和性能。作者发现表示目标应用的数据流图可分解为重复出现的通信模式，称为 motif，并据此设计集体执行与路由策略。Plaid 架构采用新型集体处理单元，可一次执行 motif 中的多个操作并共同路由相关数据依赖；Plaid 编译器则可分层映射数据流图并合理调度 motif。实验表明，与高性能时空 CGRA 基线相比，Plaid 降低 43% 功耗并节省 46% 面积；与高能效空间 CGRA 基线相比，性能提升 1.4 倍，面积节省 48%，功耗几乎不变。
Coarse-grained Reconfigurable Arrays (CGRAs) are domain-agnostic accelerators that enhance the energy efficiency of resource-constrained edge devices. The CGRA landscape is diverse, exhibiting trade-offs between performance, efficiency, and architectural specialization. However, CGRAs often overprovision communication resources relative to their modest computing capabilities. This occurs because the theoretically provisioned programmability for CGRAs often proves superfluous in practical implementations. In this paper, we propose Plaid, a novel CGRA architecture and compiler that aligns compute and communication capabilities, thereby significantly improving energy and area efficiency while preserving its generality and performance. We demonstrate that the dataflow graph, representing the target application, can be decomposed into smaller, recurring communication patterns called motifs. The primary contribution is the identification of these structural motifs within the dataflow graphs and the development of an efficient collective execution and routing strategy tailored to these motifs. The Plaid architecture employs a novel collective processing unit that can execute multiple operations of a motif and route related data dependencies together. The Plaid compiler can hierarchically map the dataflow graph and judiciously schedule the motifs. Our design achieves a 43% reduction in power consumption and 46% area savings compared to the baseline high-performance spatio-temporal CGRA, all while preserving its generality and performance levels. In comparison to the baseline energy-efficient spatial CGRA, Plaid offers a 1.4× performance improvement and a 48% area savings, with almost the same power.
DOI 原文 · arXiv · PDF（开放获取） · DBLP
@inproceedings{abs-2412-08137,
title = {Enhancing CGRA Efficiency Through Aligned Compute and Communication Provisioning},
author = {Zhaoying Li and Pranav Dangi and Chenyang Yin and Thilini Kaushalya Bandara and Rohan Juneja and Cheng Tan and Zhenyu Bai and Tulika Mitra},
booktitle = {ASPLOS},
year = {2025},
doi = {10.1145/3669940.3707230}
}