一句话：Parendi 面向 Graphcore IPU 的并行 RTL 仿真器，可扩展至 5888 核，较 x64 多核最快提升 4 倍。
随着芯片复杂度提升，单线程周期精确 RTL 仿真因单核性能停滞而难以为继。Parendi 利用 RTL 仿真固有的细粒度并行性，将其高效映射到大规模并行的 Graphcore IPU 架构。作者提出新的划分与编译技术，并系统量化同步、通信与计算开销，给出相应优化策略。在 4 个 IPU socket 上，Parendi 可扩展至 5888 核，运行大型 RTL 设计时比最强的 x64 多核系统最快提升 4 倍，表明大规模并行架构可显著加速 RTL 仿真。
Hardware development critically depends on cycle-accurate RTL simulation. However, as chip complexity increases, conventional single-threaded simulation becomes impractical due to stagnant single-core performance. Parendi is an RTL simulator that addresses this challenge by exploiting the abundant fine-grained parallelism inherent in RTL simulation and efficiently mapping it onto the massively parallel Graphcore IPU (Intelligence Processing Unit) architecture. Parendi scales up to 5888 cores on 4 Graphcore IPU sockets. It allows us to run large RTL designs up to 4x faster than the most powerful state-of-the-art x64 multicore systems. To achieve this performance, we developed new partitioning and compilation techniques and carefully quantified the synchronization, communication, and computation costs of parallel RTL simulation: The paper comprehensively analyzes these factors and details the strategies that Parendi uses to optimize them.