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P2 Hierarchical Prefetching: A Software-Hardware Instruction Prefetcher for Server Applications

层次化预取:面向服务器应用的软硬件协同指令预取器
ASPLOS Proceedings of the 30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 22025匹配度 1/10 · 论文属于计算机体系结构领域的指令预取优化,核心是软件-硬件协同的服务器应用预取器,与用户关注的 PL/AI、Agentic 程序静态分析、浮点程序分析、贝叶斯程序分析等方向基本无关。虽然提到简单软件分析,但目标是硬件预取性能而非程序分析或 LLM/Agent 交叉。引用 6 inbox
Tingji Zhang, Boris Grot, Wenjian He, Yashuai Lv, Peng Qu, Fang Su, Wenxin Wang, Guowei Zhang, Xuefeng Zhang, Youhui Zhang
crossref: 2026-09-12dblp: 2026-09-12

AI 速览

一句话:提出层次化预取,用软件分析划分粗粒度功能块(Bundle)并由轻量硬件记录重放预取,较 FDIP 平均提速 6.6%。

服务器端应用庞大的指令工作集使前端取指成为瓶颈,即便配备取指导向预取(FDIP)也难以缓解;而面向服务器场景的预取器多依赖记录—重放机制来利用指令序列的重复性,却因实际控制流与预测控制流不一致而损失覆盖率与及时性。本文提出层次化预取(Hierarchical Prefetching):先在服务器代码中识别常见的粗粒度功能块(称为 Bundle,涵盖数十至数百 KB 代码),再将其作为一个整体进行预取。该方法结合对代码的简单软件分析来形成 Bundle,以及轻量级硬件完成记录—重放式预取;由于大部分元数据保存在主存,片上存储需求不足 2KB。在 11 个流行服务器负载上的实验表明,该方法在缺失覆盖率和及时性上均显著优于先前技术,相对 FDIP 取得平均 6.6% 的性能提升。

问题
服务器应用指令工作集巨大导致前端瓶颈,已有的记录—重放式指令预取因实际与预测控制流不一致而覆盖率不足、预取不及时。
方法
通过简单的软件分析从服务器代码中抽取粗粒度功能块(Bundle,数十至数百 KB),由仅需不到 2KB 片上存储的轻量硬件以记录—重放方式整体预取这些块,元数据主要驻留主存。
评估
在 11 个流行服务器负载上,与 FDIP 等先前预取技术比较缺失覆盖率、及时性与整体性能,平均性能提升 6.6%。
原文摘要(Abstract)

The large working set of instructions in server-side applications causes a significant bottleneck in the front-end, even for high-performance processors equipped with fetch-directed instruction prefetching (FDIP). Prefetchers specifically designed for server scenarios typically rely on a record-and-replay mechanism that exploits the repetitiveness of instruction sequences. However, the efficacy of these techniques is compromised by discrepancies between actual and predicted control flows, resulting in loss of coverage and timeliness. This paper proposes Hierarchical Prefetching, a novel approach that tackles the limitations of existing prefetchers. It identifies common coarse-grained functionality blocks (called Bundles) within the server code and prefetches them as a whole. Bundles are significantly larger than typical prefetch targets, encompassing tens to hundreds of kilobytes of code. The approach combines simple software analysis of code for bundle formation and light-weight hardware for record-and-replay prefetching. The prefetcher requires under 2KB of on-chip storage by keeping most of the metadata in main memory. Experiments with 11 popular server workloads reveal that Hierarchical Prefetching significantly improves miss coverage and timeliness over prior techniques, achieving a 6.6% average performance gain over FDIP.

链接与引用

DOI 原文 · PDF(开放获取) · DBLP

BibTeX
@inproceedings{ZhangGHLQSWZZZ25,
  title = {Hierarchical Prefetching: A Software-Hardware Instruction Prefetcher for Server Applications},
  author = {Tingji Zhang and Boris Grot and Wenjian He and Yashuai Lv and Peng Qu and Fang Su and Wenxin Wang and Guowei Zhang and Xuefeng Zhang and Youhui Zhang},
  booktitle = {ASPLOS},
  year = {2025},
  doi = {10.1145/3676641.3716260}
}