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P2 C <scp>T</scp> X <scp>N</scp> L: A Software-Hardware Co-designed Solution for Efficient CXL-Based Transaction Processing

CTXNL:一种面向高效 CXL 事务处理的软硬件协同设计解决方案
ASPLOS Proceedings of the 30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 22025匹配度 1/10 · 该论文聚焦 CXL 软硬件协同与事务处理内存一致性,属于体系结构/数据库系统方向,与用户关注的静态分析、LLM/Agent 与程序分析交叉、浮点程序分析及贝叶斯程序分析没有直接关系。虽然标签涉及并发与内存模型,但不涉及用户研究画像中的核心问题。引用 12 inbox
Zhao Wang, Yiqi Chen, Cong Li, Yijin Guan, Dimin Niu, Tianchan Guan, Zhaoyang Du, Xingda Wei, Guangyu Sun
crossref: 2026-09-12dblp: 2026-09-12

AI 速览

一句话:提出软硬件协同的 CTXNL 系统,用面向事务数据弱一致性的混合一致性原语,提升 CXL 事务处理吞吐。

现代数据中心应用依赖事务处理系统,但现有多节点系统受网络开销拖累。本文提出以 Compute Express Link(CXL)作为网络替代方案,利用低延迟、缓存一致的共享内存访问。然而直接采用标准 CXL 原语会因维护跨节点缓存一致性成本过高而降低性能。为此,作者设计 CTXNL:一种软硬件协同系统,实现面向事务数据弱一致性特点的新型混合一致性原语,核心是让事务系统开发者能够按需选择性地获得数据一致性。评估在 OLTP 负载上进行,CTXNL 优于基于网络的系统,并在通用事务处理策略下相较原生 CXL 内存共享架构实现最高 2.08 倍吞吐提升。

问题
多节点事务处理受网络开销制约;直接使用标准 CXL 原语又因跨节点缓存一致性维护成本高而性能下降。
方法
提出软硬件协同的 CTXNL 系统,设计面向事务数据弱一致性的混合一致性原语,赋予开发者选择性实现数据一致性的能力。
评估
在 OLTP 工作负载上评估,与基于网络的系统及原生 CXL 内存共享架构对比,最高获得 2.08 倍吞吐提升。
原文摘要(Abstract)

Transaction processing systems are the crux for modern data-center applications, yet current multi-node systems are slow due to network overheads. This paper advocates for Compute Express Link (CXL) as a network alternative, which enables low-latency and cache-coherent shared memory accesses. However, directly adopting standard CXL primitives leads to performance degradation due to the high cost of maintaining cross-node cache coherence. To address the CXL challenges, this paper introduces CTXNL, a software-hardware co-designed system that implements a novel hybrid coherence primitive tailored to the loosely coherent nature of transactional data. The core innovation of CTXNL is empowering transaction system developers with the ability to selectively achieve data coherence. Our evaluations on OLTP workloads demonstrate that CTXNL enhances performance, outperforming current network-based systems and achieves up to 2.08x greater throughput than vanilla CXL memory sharing architectures across universal transaction processing policies.

链接与引用

DOI 原文 · DBLP

BibTeX
@inproceedings{WangCLGNGDW025,
  title = {C
            <scp>T</scp>
            X
            <scp>N</scp>
            L: A Software-Hardware Co-designed Solution for Efficient CXL-Based Transaction Processing},
  author = {Zhao Wang and Yiqi Chen and Cong Li and Yijin Guan and Dimin Niu and Tianchan Guan and Zhaoyang Du and Xingda Wei and Guangyu Sun},
  booktitle = {ASPLOS},
  year = {2025},
  doi = {10.1145/3676641.3716244}
}