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P2 <i>PhasePrint:</i> Exposing Cloud FPGA Fingerprints by Inducing Timing Faults at Runtime

PhasePrint:通过在运行时诱导时序故障暴露云 FPGA 指纹
ASPLOS Proceedings of the 30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 22025匹配度 1/10 · 该论文研究云 FPGA 的硬件指纹与运行时时序故障定位,属于硬件安全方向,与用户的程序语言、静态分析、LLM/Agent、浮点程序分析及贝叶斯程序分析等核心方向基本无关。引用 2 inbox
Jubayer Mahmod, Matthew Hicks
crossref: 2026-09-12dblp: 2026-09-12

AI 速览

一句话:提出 PhasePrint,利用运行时诱导时序故障提取云 FPGA 设备指纹,实现高精度、快速且低成本的定位。

云 FPGA 为计算密集型负载提供可扩展加速,但其硬件级访问带来数据残留与模拟域隐蔽信道等安全风险,核心前提是能定位到具体 FPGA;云厂商却限制底层硬件信息。本文提出 PhasePrint,一种完全在芯片上进行的云 FPGA 定位方法。它利用 FPGA 内部时钟合成器生成具有严格相位关系的时钟对,通过调整相位在功能正确的电路中运行时诱导时序故障,并将故障位置转化为特征向量,以刻画制造变异形成的设备签名。作者在来自 AWS 四个地理区域、300 块不同 FPGA 的数据集上训练多分类器,实现超过 99% 的定位准确率,相比现有最优方法快 13 倍、成本低 92%。

问题
云 FPGA 的多租户共享与底层硬件访问引发数据残留和隐蔽信道等风险,而厂商限制底层信息,使针对单个 FPGA 的定位(攻击或防御所需)十分困难。
方法
PhasePrint 利用 FPGA 内部时钟合成器构造相位关系可控的时钟对,在运行时诱导功能有效电路产生时序故障,并将故障位置编码为特征向量来提取设备签名。
评估
在覆盖 AWS 四个区域、300 块不同 FPGA 的数据集上训练多分类器,定位准确率超过 99%,且比 SOTA 快 13 倍、成本低 92%。
原文摘要(Abstract)

Cloud FPGAs, with their scalable and flexible nature, are rapidly gaining traction as go-to hardware acceleration platforms for compute-intensive workloads. However, their increasing adoption introduces unique security challenges. The hardware-level access that FPGAs provide leads to many vulnerabilities, including the leakage of sensitive information through data remanence and the creation of analog-domain covert channels among users. A foundational requirement in these scenarios is the ability to target an individual FPGA; knowing this, cloud vendors prevent FPGA localization by restricting access to low-level information of the underlying hardware. Beyond aiding adversaries, FPGA localization enables defenders to strategically rotate FPGA usage, preventing prolonged exposure that can lead to confidential data leakage due to long-term data remanence. This paper introduces PhasePrint, a cloud FPGA localization approach using dynamic timing faults in functionally valid circuits. PhasePrint induces timing faults in a specially crafted circuit at runtime and infers delay characteristics from the resulting error pattern---without incorporating information sources blocked by cloud vendors. PhasePrint utilizes an FPGA's internal clock synthesizer to derive a clock pair with a strict phase relationship. By adjusting the phase relationship of these clocks, PhasePrint intentionally causes timing faults at runtime that reveal manufacturing variations among FPGA chips. We transform these fault locations into feature vectors to create device signatures and train a multi-class classifier on a dataset from 300 unique FPGAs across four AWS geographic regions. This entirely on-chip signature extraction method achieves >99% accuracy, operates 13x faster, and costs 92% less than the state-of-the-art.

链接与引用

DOI 原文 · PDF(开放获取) · DBLP

BibTeX
@inproceedings{MahmodH25,
  title = {<i>PhasePrint:</i>
            Exposing Cloud FPGA Fingerprints by Inducing Timing Faults at Runtime},
  author = {Jubayer Mahmod and Matthew Hicks},
  booktitle = {ASPLOS},
  year = {2025},
  doi = {10.1145/3676641.3716012}
}