一句话：提出 TiNA 分层网络缓冲区架构，在 chiplet CPU 上按需跨 chiplet 使用 LLC 进行 DCA，降低微秒级网络延迟。
基于 chiplet 的 CPU 可低成本扩展核心与内存/IO，但跨 chiplet 访问 LLC 切片或 DRAM 控制器带来更长且方差更大的内存延迟，对微秒级网络不利。论文利用新 CPU 中鲜为人知的 Sub-NUMA Clustering（SNC）模式：默认将收包与处理限制在同一 chiplet，获得更短内存与网络延迟；但长突发收包时 SNC 给处理核心的 LLC 容量更少，使 Direct Cache Access（DCA）失效，延迟反高于非 SNC。为此提出 TiNA：由增强网卡与网络栈组成的分层网络缓冲区架构，仅在长突发时机会性使用其他 chiplet 的 LLC 切片进行 DCA。在多种网络应用与 trace 上，TiNA 相比 SNC/非 SNC 平均降低均值（尾）延迟 25%（18%）与 28%（22%）。
To manufacture a large CPU cost-effectively, the industry has begun exploiting emerging packaging technologies that integrate multiple chiplets—each comprising a subset of cores and/or memory and I/O subsystems—into a single package. However, such a CPU experiences longer memory access latency with more pronounced variance, especially when its cores in one chiplet access LLC slices or DRAM controllers in other chiplets. This creates unique challenges in μs-scale networking, which is highly sensitive to memory access latency. In this work, we start by proposing exploiting a little-known mode, known as Sub-NUMA Clustering (SNC), in the latest chiplet-based CPUs. As it restricts receiving and processing packets to a particular chiplet unless explicitly specified otherwise, it offers shorter memory access latency and, consequently, lower networking latency than the default mode (non-SNC). Nonetheless, when receiving long bursts of packets, SNC incurs higher networking latency than non-SNC, as it provides less LLC capacity for CPU cores processing the packets, making Direct Cache Access (DCA)—a commonly used CPU feature to reduce memory access latency for packet processing—ineffective. To address this drawback, we propose , a tiered network buffer architecture consisting of an enhanced NIC and networking stack, which opportunistically uses LLC slices in other chiplets for DCA only when receiving long bursts of packets. On average, reduces the mean (tail) latency by 25% (18%) and 28% (22%), compared to SNC and non-SNC, respectively, across diverse network applications and traces.
@inproceedings{AgarwalW0AK26,
title = {TiNA: Tiered Network Buffer Architecture for Fast Networking in Chiplet-based CPUs},
author = {Siddharth Agarwal and Tianchen Wang and Jinghan Huang and Saksham Agarwal and Nam Sung Kim},
booktitle = {ASPLOS},
year = {2025},
doi = {10.1145/3760250.3762224}
}