一句话：提出 XPDL 语言扩展，可由高层串行规约自动综合出支持陷阱与中断的精确异常流水线实现。
现代处理器因流水线而天然并行，实现困难。PDL 等硬件描述语言提出将高层串行规约编译为高效流水线实现，从而简化设计空间探索与推理，但此前工作不支持操作系统所需的硬件异常（陷阱、中断）。这类特性本质上是非串行的，往往需要冲刷流水线、写控制状态寄存器（CSR）或复位流水线状态，难以给出串行规约。本文提出 XPDL，扩展 PDL 以支持硬件异常，使精确异常的处理逻辑可从高层规约综合得到，同时保持 PDL 的优良性质。作者用 RISC-V 处理器设计进行评估，表明 XPDL 能灵活支持各类异常，对 CPI 没有影响，在频率和面积上仅有少量开销，并论证其实现保持了 PDL 的“一次一条指令”语义。
Modern processors are difficult to implement because pipelining makes them inherently parallel. A promising new approach, demonstrated in the PDL hardware description language, is to compile a high-level sequential specification into an efficient pipelined implementation. This high-level approach makes design-space exploration and reasoning easier. However, previous work on this approach does not support features needed for operating systems: hardware exceptions like traps and interrupts. The inherently non-sequential nature of these features makes it challenging to give them a sequential specification. They often require flushing the pipeline, writing to control state registers (CSRs), or resetting pipeline state. In this work, we develop XPDL, which extends PDL to support hardware exceptions. With this extension, logic for precise exceptions can be synthesized from a high-level specification, while maintaining the appealing properties of PDL. Using RISC-V processor designs, we demonstrate that XPDL flexibly supports exceptions with no impact on CPI (Cycles per Instructions), and minor overhead over frequency and area, and argue that the implementation preserves the one-instruction-at-a-time semantics of PDL.