一句话：提出 Canon 并行架构，用可编程 FSM 在运行时动态编排数据流，兼顾专用加速器效率与通用架构灵活性。
专用加速器在目标负载上性能出色，但依赖制造时固定的数据通路，面对新内核或不规则输入时性能脆弱；FPGA、CGRA、GPU 等可编程架构虽更灵活，却在不规则或稀疏数据下效率较低。Canon 旨在弥合二者差距：它用编译时编程的可编程有限状态机（FSM）实现动态数据驱动编排，将运行时元信息（如稀疏坐标）转换为控制指令，并为每个状态编码高层数据流；同时引入 time-lapsed SIMD，跨处理单元行多周期发射指令，形成交错流水线以摊销控制开销。实验表明，Canon 在多种 data-agnostic 与 data-driven 内核上高性能，效率接近专用加速器，同时保持通用架构的灵活性。
Domain-specific accelerators deliver exceptional performance on their target workloads through fabrication-time orchestrated datapaths. However, such specialized architectures often exhibit performance fragility when exposed to new kernels or irregular input patterns. In contrast, programmable architectures like FPGAs, CGRAs, and GPUs rely on compile-time orchestration to support a broader range of applications; but they are typically less efficient under irregular or sparse data. Pushing the boundaries of programmable architectures requires designs that can achieve efficiency and high-performance on par with specialized accelerators while retaining the agility of general-purpose architectures. We introduce Canon, a parallel architecture that bridges the gap between specialized and general purpose architectures. Canon exploits data-level and instruction-level parallelism through its novel design. First, it employs a novel dynamic data-driven orchestration mechanism using programmable Finite State Machines (FSMs). These FSMs are programmed at compile time to encode high-level dataflow per state and translate incoming meta-information (e.g., sparse coordinates) into control instructions at runtime. Second, Canon introduces a time-lapsed SIMD execution in which instructions are issued across a row of processing elements over several cycles, creating a staggered pipelined execution. These innovations amortize control overhead, allowing dynamic instruction changes while constructing a continuously evolving dataflow that maximizes parallelism. Experimental evaluation shows that Canon delivers high performance across diverse data-agnostic and data-driven kernels while achieving efficiency comparable to specialized accelerators, yet retaining the flexibility of a general-purpose architecture.
DOI 原文 · arXiv · PDF（开放获取） · DBLP
@inproceedings{abs-2602-17119,
title = {A Data-Driven Dynamic Execution Orchestration Architecture},
author = {Zhenyu Bai and Pranav Dangi and Rohan Juneja and Zhaoying Li and Zhanglu Yan and Huiying Lan and Tulika Mitra},
booktitle = {ASPLOS},
year = {2025},
doi = {10.1145/3760250.3762226}
}