一句话：评估在 GPU SIMT 核中集成 CHERI 能力内存保护的可行性，并提出显著降低寄存器、面积与执行开销的技术。
各国政府日益建议软件厂商采用内存安全语言与技术以抵御攻击，这给提供 CUDA/OpenCL 等不安全 C/C++ 编程环境的 GPU 厂商带来压力。CHERI 是一种被推荐的能力硬件增强内存安全技术，但将其引入 GPU 架构的可行性尚不明确。本文扩展一个开源、可综合的 SIMT 核及其类 CUDA 编程环境以支持 CHERI，并针对 SIMT 设计提出多项降低开销的技术。实验表明，寄存器文件存储开销从 103% 降至 7%，逻辑面积开销降低 44%，约等于每条向量通道增加一个乘法器的成本，执行时间开销降至 1.6%。这说明 CHERI 可为 GPU 提供可行且高效的内存安全路径，同时避免替换既有编程实践。
Governments are increasingly advising software manufacturers to employ memory-safe languages and technologies to combat adversarial attacks on modern computing infrastructure. This introduces pressures across the entire computing industry, including GPU vendors who provide implementations of unsafe C/C++-based languages, such as CUDA and OpenCL, for programming the devices they produce. One of the memory-safety technologies being recommended is Capability Hardware Enhanced RISC Instructions (CHERI). CHERI builds strong and efficient memory safety into underlying instruction-set architectures allowing continued, but memory-safe, use of C/C++-based languages on top. In this paper, we evaluate the feasibility of incorporating CHERI into GPU architectures by extending a prototype, open-source, synthesisable, SIMT core and CUDA-like programming environment with support for CHERI. We present techniques to considerably ameliorate the costs of CHERI in SIMT designs, reducing register-file storage overheads from 103% to 7%, logic-area overheads by 44% to a cost comparable to one additional multiplier per vector lane, and execution-time overheads to 1.6%. With the proposed techniques, CHERI offers a viable path to strong and efficient GPU memory safety, while avoiding the need to replace established programming practices.
@inproceedings{NaylorJMMM026,
title = {CHERI-SIMT: Implementing Capability Memory Protection in GPUs},
author = {Matthew Naylor and Alexandre Joannou and A. Theodore Markettos and Paul Metzger and Simon W. Moore and Timothy M. Jones},
booktitle = {ASPLOS},
year = {2025},
doi = {10.1145/3760250.3762234}
}