一句话：将 RTL 仿真重构为稀疏张量代数问题，以张量表示电路和仿真内核，缓解编译开销与前端瓶颈，性能比肩 Verilator。
CPU 上的 RTL 仿真是硬件设计中的长期瓶颈：当前先进仿真器把电路直接嵌入仿真二进制，导致编译时间长、执行受 CPU 前端限制并承受严重的指令缓存压力。本文提出 RTeAAL Sim，将 RTL 仿真重新表述为稀疏张量代数问题：把 RTL 电路表示为张量、把仿真表示为稀疏张量代数内核，从而将仿真行为与二进制大小解耦，并使 RTL 仿真能够受益于已有充分研究的张量代数优化。评估表明，即便原型只采用其中部分优化，也已缓解编译开销与前端压力，并在多种 CPU 与 ISA 上取得与高度优化的 Verilator 相竞争的性能。
RTL simulation on CPUs remains a persistent bottleneck in hardware design. State-of-the-art simulators embed the circuit directly into the simulation binary, resulting in long compilation times and execution that is fundamentally CPU frontend-bound, with severe instruction-cache pressure. This work proposes RTeAAL Sim, which reformulates RTL simulation as a sparse tensor algebra problem. By representing RTL circuits as tensors and simulation as a sparse tensor algebra kernel, RTeAAL Sim decouples simulation behavior from binary size and makes RTL simulation amenable to well-studied tensor algebra optimizations. We demonstrate that a prototype of our tensor-based simulator, even with a subset of these optimizations, already mitigates the compilation overhead and frontend pressure and achieves performance competitive with the highly optimized Verilator simulator across multiple CPUs and ISAs.
DOI 原文 · arXiv · PDF（开放获取） · DBLP
@inproceedings{ZhuCFN26,
title = {RTeAAL Sim: Using Tensor Algebra to Represent and Accelerate RTL Simulation},
author = {Yan Zhu and Boru Chen and Christopher W. Fletcher and Nandeeka Nayak},
booktitle = {ASPLOS},
year = {2026},
doi = {10.1145/3779212.3790214}
}