一句话：提出跨层韧性优化框架 CREATE，通过电路、模型与应用协同降低具身 AI 能耗并提升可靠性。
具身 AI 系统常结合 LLM 规划器与 RL 控制器完成复杂任务，但高算力需求使电池供电设备难以部署。降低工作电压可提升能效，却会引入位错误并导致任务失败。本文提出 CREATE，一种利用不同层异构韧性的跨层能量-可靠性协同优化设计原则。作者首次系统错误注入现代具身 AI 系统，发现其固有且异质的容错能力。CREATE 在电路层加入异常检测与清除机制以消除离群错误；在模型层提出权重旋转增强规划算法以提升 LLM 规划器容错性；在应用层引入自主性自适应电压调节，并协同设计调压电路支持在线调压。实验显示，在不损失任务质量下，CREATE 平均节省 40.6% 计算能耗，较现有技术节省 35.0%，芯片级能耗降低 29.5%–37.3%，电池寿命提升约 15%–30%。
Embodied Artificial Intelligence (AI) has recently attracted significant attention as it bridges AI with the physical world. Modern embodied AI systems often combine a Large Language Model (LLM)-based planner for high-level task planning and a reinforcement learning (RL)-based controller for low-level action generation, enabling embodied agents to tackle complex tasks in real-world environments. However, deploying embodied agents remains challenging due to their high computation requirements, especially for battery-powered local devices. Although techniques like lowering operating voltage can improve energy efficiency, they can introduce bit errors and result in task failures. In this work, we propose CREATE, a general design principle that leverages heterogeneous resilience at different layers for synergistic energy-reliability co-optimization. For the first time, we conduct a comprehensive error injection study on modern embodied AI systems and observe an inherent but heterogeneous fault tolerance. Building upon these insights, we develop an anomaly detection and clearance mechanism at the circuit level to eliminate outlier errors. At the model level, we propose a weight-rotation-enhanced planning algorithm to improve the fault tolerance of the LLM-based planner. Furthermore, we introduce an application-level technique, autonomy-adaptive voltage scaling, to dynamically adjust the operating voltage of the controllers. The voltage scaling circuit is co-designed to enable online voltage adjustment. Extensive experiments demonstrate that without compromising task quality, CREATE achieves 40.6% computational energy savings on average over nominal-voltage baselines and 35.0% over prior-art techniques. This further leads to 29.5% to 37.3% chip-level energy savings and approximately a 15% to 30% improvement in battery life.
DOI 原文 · arXiv · PDF（开放获取） · DBLP
@inproceedings{abs-2601-14140,
title = {CREATE:
<u>C</u>
ross-Layer Resilience Characterization and Optimization for Efficient yet
<u>R</u>
eliable
<u>E</u>
mbodied
<u>A</u>
I Sys
<u>te</u>
ms},
author = {Tong Xie and Yijiahao Qi and Jinqi Wen and Zishen Wan and Yanchi Dong and Zihao Wang and Shaofei Cai and Yitao Liang and Tianyu Jia and Yuan Wang and Runsheng Wang and Meng Li},
booktitle = {ASPLOS},
year = {2026},
doi = {10.1145/3779212.3790147}
}