一句话：提出 CounterPoint 框架，用性能计数器数据检验微架构模型并定位可解释偏差的硬件特征。
硬件事件计数器有望揭示性能瓶颈和微架构行为，但其规格模糊、设计不透明、复用噪声大，导致数据难以解释。CounterPoint 将用户指定的微架构模型表示为 path Decision Diagrams，并检验其与性能计数器数据的一致性；当出现不一致时，利用多维计数器置信区域缓解复用噪声，并定位可解释偏差的合理微架构特征。作者以 Haswell 内存管理单元为案例，发现多个未文档化或文档不足的行为，包括 load-store queue 侧 TLB 预取器、合并的 page table walker、可中止的 page table walk 等。该工作帮助专家协调嘈杂的性能计数器测量与微架构心智模型，并揭示隐藏硬件特性。
Hardware event counters offer the potential to reveal not only performance bottlenecks but also detailed microarchitectural behavior. In practice, this promise is undermined by their vague specifications, opaque designs, and multiplexing noise, making event counter data hard to interpret. We introduce CounterPoint, a framework that tests user-specified microarchitectural models — expressed as ?path Decision Diagrams — for consistency with performance counter data. When mismatches occur, CounterPoint pinpoints plausible microarchitectural features that could explain them, using multi-dimensional counter confidence regions to mitigate multiplexing noise. We apply CounterPoint to the Haswell Memory Management Unit as a case study, shedding light on multiple undocumented and underdocumented microarchitectural behaviors. These include a load–store queue-side TLB prefetcher, merging page table walkers, abortable page table walks, and more. Overall, CounterPoint helps experts reconcile noisy hardware performance counter measurements with their mental model of the microarchitecture - uncovering subtle, previously hidden hardware features along the way.
@inproceedings{paperbot10557,
title = {CounterPoint: Using Hardware Event Counters to Refute and Refine Microarchitectural Assumptions},
author = {Nick Lindsay and Caroline Trippel and Anurag Khandelwal and Abhishek Bhattacharjee},
booktitle = {ASPLOS},
year = {2026},
doi = {10.1145/3779212.3790145}
}