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P2 Arancini: A Hybrid Binary Translator for Weak Memory Model Architectures

Arancini:面向弱内存模型架构的混合二进制翻译器
ASPLOS Proceedings of the 31st ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 22026匹配度 2/10 · 该论文属于传统程序语言与形式验证领域,涉及二进制翻译、弱内存模型和形式化验证,但不涉及 LLM/Agent、静态分析在机器学习系统中的应用、浮点程序分析或贝叶斯程序分析。虽然形式验证与用户的部分兴趣有交集,但整体研究方向与用户画像核心问题匹配度很低。引用 2 inbox
Sebastian Reimers, Dennis Sprokholt, Martin Fink, Theofilos Augoustis, Simon Kammermeier, Rodrigo C. O. Rocha, Tom Spink, Redha Gouicem, Soham Chakraborty, Pramod Bhatotia
crossref: 2026-09-12dblp: 2026-09-12

AI 速览

一句话:提出 Arancini 混合二进制翻译器,借统一 IR 与形式验证的强到弱内存映射,为弱内存架构实现正确、完整且高效的跨架构仿真。

跨架构二进制翻译在异构计算中日益重要,但强内存模型(如 x86-64)到弱内存模型(Arm/RISC-V)的并发程序翻译存在正确性风险;静态翻译完整性不足,动态翻译性能受限。作者提出 Arancini 混合二进制翻译器,核心包括统一静态与动态翻译的 ArancinIR、形式化 ArancinIR 内存模型、形式验证 x86-64 到 Arm/RISC-V 的强到弱映射方案,并实现完整高效的翻译器。评估使用多线程基准与 Arm/RISC-V 后端,表明其比 QEMU 系翻译器最高快 5 倍,同时保证正确性与完整性。该工作是首个由形式证明指导、确保强内存客户机在弱内存宿主上正确执行的混合翻译器,也是首个处理 Arm 混合大小访问的翻译器。

问题
如何在异构架构间为未修改的并发二进制提供正确、完整且高效的跨架构仿真,尤其是解决 x86-64 等强内存模型到 Arm/RISC-V 等弱内存模型的 strong-on-weak 正确性问题。
方法
提出 Arancini 混合二进制翻译器,设计统一 IR ArancinIR,形式化其内存模型并验证 x86-64 到 Arm/RISC-V 的映射方案,并在完整翻译器中实现这些映射。
评估
使用多线程基准套件,在 Arm 与 RISC-V 两个后端上与 QEMU 系翻译器对比,显示最高 5 倍加速且保证正确性与完整性。
原文摘要(Abstract)

Binary translation is a powerful approach to support cross-architecture emulation of unmodified binaries in increasingly heterogeneous computing environments. However, binary translation systems face correctness issues, due to the strong-on-weak memory model mismatch (e.g., from x86-64 to Arm/RISC-V) for concurrent programs. Besides, the current landscape of binary translation systems is fundamentally limited in terms of completeness for static systems and performance for dynamic ones. To address these limitations, we propose Arancini, a hybrid binary translator system designed and implemented from the ground up that strives for correct, complete, and efficient emulation for weak memory model architectures. Our system makes three foundational contributions to achieve these design goals: ArancinIR, a unified intermediate representation for static and dynamic binary translators; a formalization of ArancinIR,'s memory model and formally verified mapping schemes from x86-6 to Arm and RISC-V, to ensure strong-on-weak correctness; and Arancini, a complete and performant hybrid binary translator, implementing the verified mapping schemes for correctness. We evaluate Arancini using a multi-threaded benchmark suite with two backends (Arm and RISC-V), and show that Arancini can be up to 5× faster than QEMU--based translators while ensuring correctness and completeness. To our knowledge, Arancini is the first hybrid binary translator whose implementation is guided by formal proofs, to ensure correct execution of strong memory guests on weak memory hosts. It is also the first translator to address mixed-sized accesses for Arm targets.

链接与引用

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BibTeX
@inproceedings{ReimersS0AKRSG026,
  title = {Arancini: A Hybrid Binary Translator for Weak Memory Model Architectures},
  author = {Sebastian Reimers and Dennis Sprokholt and Martin Fink and Theofilos Augoustis and Simon Kammermeier and Rodrigo C. O. Rocha and Tom Spink and Redha Gouicem and Soham Chakraborty and Pramod Bhatotia},
  booktitle = {ASPLOS},
  year = {2026},
  doi = {10.1145/3779212.3790127}
}