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P2 Reducing T Gates with Unitary Synthesis

利用酉合成减少 T 门
ASPLOS Proceedings of the 31st ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 22026匹配度 1/10 · 论文关注量子容错电路中的酉合成与 T 门优化,属于量子编译/综合方向;与用户研究的 PL→AI、AI→PL、浮点程序分析及贝叶斯程序分析等核心方向均无直接关联。引用 22 inbox
Tianyi Hao, Amanda Xu, Swamit Tannu
crossref: 2026-09-12dblp: 2026-09-12arxiv: 2026-09-12

AI 速览

一句话:提出 TRASYN,直接合成任意单量子比特酉,避免单独 Rz 分解,显著减少容错电路的 T 门与 Clifford 门。

量子纠错对实用量子计算至关重要,但容错门操作开销很大,其中 T 门因依赖 magic state distillation 尤其昂贵。许多量子算法需要 Rx/Rz 等任意单量子比特旋转,必须分解为 T 与 Clifford 门;Rx 与 Rz 常可融合为 U3 酉,但 gridsynth 等已有方法依赖间接分解并单独处理 Rz,导致 T 数量约三倍增加。本文提出 TRASYN,一种基于张量网络搜索的容错合成算法,可直接原生合成任意单量子比特 U3 酉,避免单独 Rz 分解带来的开销。在 187 个代表性基准上,与基于 gridsynth 的电路合成相比,TRASYN 将 T 门数量最多减少 3.5 倍、Clifford 门最多减少 7 倍,整体电路 infidelity 最多改善 4 倍,同时降低近似误差。

问题
容错量子电路中 T 门依赖 magic state distillation 而代价高昂,而任意单量子比特旋转需分解为 T 与 Clifford 门;已有合成方法间接分解并单独处理 Rz,导致 T 数量增加。
方法
提出 TRASYN,利用张量网络搜索直接原生合成任意单量子比特 U3 酉,避免单独的 Rz 分解,以同时优化 T 门、Clifford 门和近似误差。
评估
在 187 个代表性基准上与 gridsynth 类合成比较,T 门最多减少 3.5 倍,Clifford 门最多减少 7 倍,整体电路 infidelity 最多改善 4 倍。
原文摘要(Abstract)

Quantum error correction is essential for achieving practical quantum computing but has a significant computational overhead. Among fault-tolerant (FT) gate operations, non-Clifford gates, such as T, are particularly expensive due to their reliance on magic state distillation. These costly T gates appear frequently in FT circuits as many quantum algorithms require arbitrary single-qubit rotations, such as Rx and Rz gates, which must be decomposed into a sequence of T and Clifford gates. In many quantum circuits, Rx and Rz gates can be fused to form a single U3 unitary. However, existing synthesis methods, such as gridsynth, rely on indirect decompositions, requiring separate Rz decompositions that result in a threefold increase in T count. This work presents TensoR-based Arbitrary unitary SYNthesis (TRASYN), a novel FT synthesis algorithm that directly synthesizes arbitrary single-qubit unitaries, avoiding the overhead of separate Rz decompositions. By leveraging tensor network-based search, our approach enables native U3 synthesis, reducing the T count, Clifford gate count, and approximation error. Compared to gridsynth-based circuit synthesis, for 187 representative benchmarks, our design reduces the T count by up to 3.5 ×, and Clifford gates by 7 ×, resulting in up to 4 × improvement in overall circuit infidelity.

链接与引用

DOI 原文 · arXiv · PDF(开放获取) · DBLP

BibTeX
@inproceedings{0003XT26,
  title = {Reducing T Gates with Unitary Synthesis},
  author = {Tianyi Hao and Amanda Xu and Swamit Tannu},
  booktitle = {ASPLOS},
  year = {2026},
  doi = {10.1145/3779212.3790210}
}