一句话：提出 BitRed，用可编程 RISC-V ISA 扩展将非均匀位级稀疏加速转化为灵活调度，显著提速并平衡负载。
位级稀疏性（BLS）非均匀且动态，导致并行加速器负载不均；Bitlet 等位交织范式受刚性数据通路和通道间失衡限制。本文提出 BitRed，以可编程自适应位交织为核心，将加速拆解为预处理 cal.pre、动态负载均衡的自适应蒸馏 cal.adis 与 PDP 最优归约 cal.red 三组正交 RISC-V ISA 扩展，把硬件难题转为灵活调度。在多种基准（相对 SCNN 归一化）上，BitRed 较 Bitlet 最高加速 9.4×、较 BitWave 5.6×，推理效率最高为 Bitlet 的 7.6×；28nm 下面积 5.072mm²，功耗 550.43mW（float32）至 457.90mW（8b），较 A100/Jetson Orin 32GB 最高提升 18.9×/13.5×。
The non-uniform and dynamic nature of Bit-Level Sparsity (BLS) poses a critical load-imbalance challenge for parallel hardware accelerators. While the Bit-Interleaving paradigm, represented by state-of-the-art accelerators like Bitlet, shows promise, it is fundamentally constrained by a rigid datapath and severe inter-channel load imbalance. This paper introduces BitRed, an accelerator that embodies a new ''programmable adaptive bit-interleaving'' philosophy. Rather than a monolithic design, BitRed's core is an Adaptive-Sparse Processing Unit (ASPU) that deconstructs the acceleration process into a set of orthogonal RISC-V ISA extensions for pre-processing (cal.pre), adaptive distillation with dynamic load balancing (cal.adis), and PDP-optimal reduction (cal.red). By transforming a rigid hardware problem into a flexible scheduling problem, this ISA-based approach provides a fundamentally more adaptable and extensible solution. Empirical studies on a broad set of benchmarks highlight the following results (normalized to a SCNN baseline): (1) up to 9.4× speedup over the Bitlet, and 5.6× over the latest bit-serial SOTA BitWave; (2) up to 7.6× higher inference efficiency than Bitlet on representative models; (3) 5.072mm2 area and scalable power consumption from 550.43mW (float32) to 495.12mW (16b) and 457.90mW (8b) @28nm TSMC; and (4) high versatility across precisions, and up to 18.9×13.5× higher than NVIDIA A100 and Jetson Orin 32GB, demonstrating significant competitiveness against GPUs.
@inproceedings{LiuLZLWW0WFYFA26,
title = {BitRed: Taming Non-Uniform Bit-Level Sparsity with a Programmable RISC-V ISA for DNN Acceleration},
author = {Yanhuan Liu and Wenming Li and Kunming Zhang and Yuqun Liu and Siao Wen and Lexin Wang and Tianyu Liu and Haibin Wu and Zhihua Fan and Xiaochun Ye and Dongrui Fan and Xuejun An},
booktitle = {ASPLOS},
year = {2026},
doi = {10.1145/3779212.3790132}
}