一句话：提出 DIP，在分派阶段用时间比例归因与采样生成每指令周期栈，低开销高精度诊断指令进入乱序窗口的瓶颈。
尽管加速器不断进步，受 Amdahl 定律制约，单线程性能依然关键，开发者常需指令级性能分析。已有的每指令周期栈在提交阶段（PICSC）采集，只反映指令离开乱序执行窗口的效率，无法解释指令进入（ingress）窗口时的延迟问题。本文提出分派阶段剖析（DIP），将按时间比例的分派阶段归因策略与统计采样结合，既能报告每条静态指令对分派时间的贡献，又能列出其延迟进入的原因。DIP 实现简单、开销低，仅需 49 字节存储、约 1% 执行时间开销，平均剖析误差 5.2%，显著优于 AMD IBS、Arm SPE 与 IBM RIS 中先进分派标记方法的 26.9% 误差。在 22 个 SPEC2017 基准中，18 个同时存在 ingress 与 egress 问题，说明 PICSD 与 PICSC 常需并用；作者还借助 DIP 的 PICSD 优化 fotonik3d，获得 8.5% 的性能提升。
Despite continuous accelerator improvements, high single-thread performance remains crucial due to Amdahl's Law. With technology scaling slowing, developers must produce code that is as performant as possible, which often involves instruction-level performance analysis. Such analysis can be visualized as Per-Instruction Cycle Stacks (PICS), which, when created at the commit stage of the processor, report each static instruction's contribution to overall execution time and capture the performance events it was subject to. Sadly, PICS at commit (PICSC) often cannot explain performance because they solely capture how effectively instructions egress from the processor core's out-of-order execution window. In contrast, developers must typically also gain insight into how efficiently instructions ingress into the execution window to fully understand application performance. PICSC must hence be complemented by PICS at dispatch (PICSD) because execution window ingress issues result in specific instructions exhibiting high dispatch latencies. We therefore propose dispatch-time profiling (DIP), which combines time-proportional at dispatch attribution policies with statistical sampling to accurately report each static instruction's contribution to dispatch time as well as list the reason(s) for delayed ingress. DIP is simple to implement and incurs low overhead, i.e., storage and execution time and overheads of 49 bytes and ~1%, respectively, while delivering high accuracy (average profile error of 5.2%). This is a significant improvement over the 26.9% error of state-of-the-art dispatch-tagging as implemented in AMD IBS, Arm SPE, and IBM RIS. We demonstrate that needing PICSD and PICSC is the common case by showing that 18 out of our 22 SPEC2017 benchmarks simultaneously exhibit both ingress and egress issues. Additionally, we leverage DIP's PICSD to optimize the fotonik3d benchmark, improving its performance by 8.5%.
@inproceedings{SantanaREJ26,
title = {Chips Need DIP: Time-Proportional Per-Instruction Cycle Stacks at Dispatch},
author = {Silvio Campelo de Santana and Joseph Rogers and Lieven Eeckhout and Magnus Jahre},
booktitle = {ASPLOS},
year = {2026},
doi = {10.1145/3779212.3790139}
}