一句话：提出拓扑感知的表面码编译方法，并据此优化 QCCD 阱容量等架构参数，发现双离子小阱最优。
囚禁离子（TI）量子比特是领先的量子计算平台，当前系统不足 60 个量子比特，而 QCCD 模块化架构有望扩展规模。近term系统错误率（10^-3 至 10^-4）与实用应用需求（低于 10^-9）之间存在巨大差距，必须借助量子纠错（QEC）构建由多个物理量子比特组成的逻辑量子比特。然而，目前尚不清楚 QCCD 系统应如何设计才能实现实用规模的 QEC。本文研究如何在 QCCD 系统上高效实现表面码这一标准 QEC 方案。为此，作者开发了一种近最优的拓扑感知编译方法，其逻辑时钟速度平均比现有 QCCD 编译器快 3.8 倍，并用该编译器考察硬件阱容量、连通性和电极布线选择如何针对表面码实现进行优化。结果表明，仅容纳两个离子的较小阱在性能最优性和硬件效率两方面都出乎意料地理想，这与以往认为较大阱（20-30 个离子）更优的直觉相反，可为未来系统设计提供参考。
Trapped ion (TI) qubits are a leading quantum computing platform. Current TI systems have less than 60 qubits, but a modular architecture known as the Quantum Charge-Coupled Device (QCCD) is a promising path to scale up devices. There is a large gap between the error rates of near-term systems (10-3 to 10-4) and the requirements of practical applications (below 10-9). To bridge this gap, we require Quantum Error Correction (QEC) to build logical qubits that are composed of multiple physical qubits. While logical qubits have been demonstrated on TI qubits, these demonstrations are restricted to small codes and systems. There is no clarity on how QCCD systems should be designed to implement practical-scale QEC. This paper studies how surface codes, a standard QEC scheme, can be implemented efficiently on QCCD-based systems. To examine how architectural parameters of a QCCD system can be tuned for surface codes, we develop a near-optimal topology-aware compilation method that outperforms existing QCCD compilers by an average of 3.8X in terms of logical clock speed. We use this compiler to examine how hardware trap capacity, connectivity and electrode wiring choices can be optimised for surface code implementation. In particular, we demonstrate that small traps of two ions are surprisingly ideal from both a performance-optimal and hardware-efficiency standpoint. This result runs counter to prior intuition that larger traps (20-30 ions) would be preferable, and has the potential to inform design choices for upcoming systems.