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P2 Co-Exploration of RISC-V Processor Microarchitectures and FreeRTOS Extensions for Lower Context-Switch Latency

面向更低上下文切换延迟的 RISC-V 处理器微架构与 FreeRTOS 扩展协同探索
ASPLOS Proceedings of the 31st ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 22026匹配度 1/10 · 该论文研究 RISC-V 微架构与 FreeRTOS 硬件加速以降低上下文切换延迟,属于嵌入式实时系统与体系结构方向,与用户关注的形式化/静态分析、LLM/Agent、浮点程序分析和贝叶斯程序分析均无直接交集。引用 4 inbox
Markus Scheck, Tammo Mürmann, Andreas Koch
crossref: 2026-09-12dblp: 2026-09-12

AI 速览

一句话:提出可配置硬件加速单元 RTOSUnit 并与 FreeRTOS 扩展协同,将 RISC-V 嵌入式系统的上下文切换延迟最多降低 76% 并消除抖动。

嵌入式实时系统必须在外界事件后的严格时限内响应,以保证安全与可靠。RTOS 虽通过多任务抽象简化开发,却引入任务切换延迟与抖动,削弱时序可预测性。本文提出 RTOSUnit:一个可配置的硬件加速单元,并与 FreeRTOS 扩展协同设计,以降低上下文切换延迟与抖动。作者将其集成到三种复杂度不同的 RISC-V 核中验证可移植性,并提供从轻量调度加速到完整上下文切换与预加载的多种配置。在 22nm ASIC 实现下,平均上下文切换延迟最多降低 76%,部分核上可完全消除抖动;面积开销从可忽略到 44%,所有配置均保持可用的工作频率与功耗包络。该开源设计为面向实时调度的硬件辅助方案提供了灵活基础。

问题
嵌入式实时系统中,RTOS 的任务切换延迟与抖动会破坏时序可预测性,需在降低响应时间的同时支持可靠的最坏情况时序分析。
方法
设计可配置的硬件加速单元 RTOSUnit 并与 FreeRTOS 扩展协同设计,将其集成到三种复杂度不同的 RISC-V 核中,支持从轻量调度加速到完整上下文切换与上下文预加载的多种配置。
评估
在 22nm ASIC 实现上评估:平均上下文切换延迟最多降低 76%,部分核上可完全消除抖动;面积开销从可忽略到 44%,所有配置仍保持可用的工作频率与功耗包络。
原文摘要(Abstract)

Embedded real-time systems must respond to external events within tightly bounded timeframes to ensure safety, correctness, and reliability. While Real-Time Operating Systems (RTOSes) ease the development of complex applications by providing abstractions for multi-tasked execution, they introduce overheads in the form of task switching latency and jitter, which impact timing predictability. Minimizing these effects is essential for reducing response times and enabling robust worst-case timing analysis. We present RTOSUnit, a configurable hardware acceleration unit designed to reduce context-switch latency and jitter in embedded real-time systems. By integrating the RTOSUnit into three RISC-V cores of varying complexity, we demonstrate its portability. Through a range of configurations, from lightweight scheduling acceleration to full context-switch and -preloading support, RTOSUnit achieves up to 76% reduction in mean context-switch latency and can be configured to completely eliminate jitter on selected cores. Area overheads in 22nm ASIC implementations range from negligible (within EDA tool heuristics noise) to 44\,%, with all configurations maintaining viable operating frequencies and power envelopes suitable for embedded systems. RTOSUnit offers a flexible and efficient, open-source. https://github.com/esa-tu-darmstadt/RTOSUnit_Integration foundation for hardware-assisted real-time scheduling, paving the way for broader integration into future embedded SoCs.

链接与引用

DOI 原文 · PDF(开放获取) · DBLP

BibTeX
@inproceedings{ScheckM026,
  title = {Co-Exploration of RISC-V Processor Microarchitectures and FreeRTOS Extensions for Lower Context-Switch Latency},
  author = {Markus Scheck and Tammo Mürmann and Andreas Koch},
  booktitle = {ASPLOS},
  year = {2026},
  doi = {10.1145/3779212.3790141}
}