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P2 Reconfigurable Quantum Instruction Set Computers for High Performance Attainable on Hardware

可重构量子指令集计算机:在硬件上实现可达的高性能
ASPLOS Proceedings of the 31st ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 22026匹配度 2/10 · 论文聚焦量子指令集、微架构与量子编译器,属于量子体系结构和编译优化,与用户核心关注的 LLM/Agent、静态分析、浮点程序分析及贝叶斯程序分析基本无关;仅在“语言与体系结构/编译器”层面有非常宽泛的关联。引用 3 inbox
Zhaohui Yang, Dawei Ding, Qi Ye, Cupjin Huang, Jianxin Chen, Yuan Xie
crossref: 2026-09-12dblp: 2026-09-12arxiv: 2026-09-12

AI 速览

一句话:提出 ReQISC:统一微架构可等价直接实现任意二量子比特门并配套端到端编译器,首次让连续量子指令集的理论优势在硬件上落地。

量子硬件性能仍受限,一条关键路径是把量子 ISA 扩展到比标准 CNOT 保真度更高、合成能力更强的基门;但这会大幅增加门标定开销并给编译优化带来挑战,因此现有更具表达力的 ISA(即便是连续门集合)多停留在概念验证阶段。本文提出“可重构量子指令集计算机”(ReQISC),包含两部分:(1) 统一微架构,可在给定任意二量子比特耦合哈密顿量下直接等价实现任意 2Q 门(即模掉 1Q 旋转的 SU(4)),并达到理论最优门时长;(2) 面向 ReQISC 原语的编译框架,涵盖程序感知的高层表示精化 pass、程序无关的激进电路级优化 pass,以及 SU(4) 感知的路由 pass 以最小化硬件映射开销。作者还给出硬件实现细节,从脉冲控制与标定两方面论证该门方案的可行性。在主流 flux-tunable transmon 上,基于 SU(4) 的 ISA 实现任意 2Q 门的平均脉冲时长相比常规 CNOT/CZ 方案降低 4.97 倍;配合端到端编译器,ReQISC 在 2Q 门数、电路深度、脉冲时长、量子比特映射开销和程序保真度损失等指标上均显著优于基于 CNOT 的传统 ISA、当前最优编译器及其脉冲实现方案。

问题
量子硬件性能受限于标准 CNOT/CZ 基门,而扩展为更具表达力的连续量子 ISA 又会带来巨大的门标定开销与编译优化难题,使这类 ISA 长期停留于概念验证。
方法
提出 ReQISC:一是可直接等价实现任意 2Q 门(SU(4) 模 1Q 旋转)并达到理论最优门时长的统一微架构,二是包含程序感知精化、程序无关电路级优化和 SU(4) 感知路由的端到端编译框架,并给出脉冲控制与标定的硬件实现方案。
评估
在主流 flux-tunable transmon 上对比常规 CNOT/CZ 方案、当前最优编译器与脉冲实现,测量任意 2Q 门的平均脉冲时长(降低 4.97 倍)、2Q 门数、电路深度、映射开销与程序保真度损失。
原文摘要(Abstract)

Despite remarkable milestones in quantum computing, the performance of current quantum hardware remains limited. One critical path to higher performance is to expand the quantum ISA with basis gates that have higher fidelity and greater synthesis capabilities than the standard CNOT. However, this substantially increases gate calibration overhead and introduces challenges in compiler optimization. Consequently, although more expressive ISAs (even complex, continuous gate sets) have been proposed, they still remain primarily proofs-of-concept and have not been widely adopted. To move beyond these hurdles and unlock the performance gains offered by expressive continuous ISAs, we introduce the concept of ''reconfigurable quantum instruction set computers'' (ReQISC). It incorporates (1) a unified microarchitecture capable of directly implementing arbitrary 2Q gates equivalently, i.e., SU(4) modulo 1Q rotations, with theoretically optimal gate durations given any 2Q coupling Hamiltonian and (2) a compilation framework tailored to ReQISC primitives for end-to-end synthesis and optimization, comprising a program-aware pass that refines high-level representations, a program-agnostic pass for aggressive circuit-level optimization, and an SU(4)-aware routing pass that minimizes hardware mapping overhead. We detail the hardware implementation to demonstrate the feasibility of this superior gate scheme in terms of both pulse control and calibration. By leveraging the expressivity of SU(4) and the time minimality realized by the underlying microarchitecture, the SU(4)-based ISA achieves remarkable performance, with a 4.97-fold reduction in average pulse duration to implement arbitrary 2Q gates, compared to the usual CNOT/CZ scheme on mainstream flux-tunable transmons. Supported by the end-to-end compiler, ReQISC outperforms the conventional CNOT-based ISA, state-of-the-art compiler, and pulse implementation counterparts by significantly reducing 2Q gate count, circuit depth, pulse duration, qubit mapping overhead, and program fidelity losses. For the first time, ReQISC makes the theoretical benefits of continuous ISAs practically feasible.

链接与引用

DOI 原文 · arXiv · PDF(开放获取) · DBLP

BibTeX
@inproceedings{YangD0HCX26,
  title = {Reconfigurable Quantum Instruction Set Computers for High Performance Attainable on Hardware},
  author = {Zhaohui Yang and Dawei Ding and Qi Ye and Cupjin Huang and Jianxin Chen and Yuan Xie},
  booktitle = {ASPLOS},
  year = {2026},
  doi = {10.1145/3779212.3790208}
}