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P2 ICARUS: Criticality and Reuse based Instruction Caching for Datacenter Applications

ICARUS:面向数据中心应用的基于关键性与重用的指令缓存
ASPLOS Proceedings of the 31st ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 22026匹配度 0/10 · 论文研究的是数据中心应用下基于关键性和重用行为的 L2 指令缓存替换策略,属于计算机体系结构/微架构方向,与用户关注的程序语言、静态分析、LLM/Agent、浮点程序分析和贝叶斯程序分析等研究方向完全无关。引用 2 inbox
Vedant Kalbande, Hrishikesh Jedhe Deshmukh, Alberto Ros, Biswabandan Panda
crossref: 2026-09-12dblp: 2026-09-12

AI 速览

一句话:ICARUS 利用分支历史上下文识别关键指令行并结合重用行为改进 L2 替换策略,缓解数据中心应用的前端瓶颈。

数据中心应用代码规模庞大,即使采用解耦前端仍会遭遇前端 CPU 瓶颈,其中 L2 指令缺失导致的解码饥饿是主要成因。现有基于前端关键性的 L2 替换策略(如 EMISSARY)试图保留引发解码饥饿的关键指令行,但作者观察到只有 28.32% 的关键行能保持关键性,大量关键指令行表现出动态行为。为此,ICARUS 将分支历史作为上下文信息来改进关键指令行检测,因为指令行的重用距离会随导致该次取指的分支历史而变化;同时,由于关键行与非关键行的重用行为不同,ICARUS 在替换决策中同时考虑 L2 关键性与指令行重用。在 12 个数据中心应用上,ICARUS 平均比 TPLRU 提升 5.6%,最高达 51%,而 EMISSARY 仅提升 2.2%;作者还验证了其在不同 L1I/L2 缓存容量下以及存在硬件预取器时的鲁棒性。

问题
数据中心应用代码 footprint 巨大,L2 指令缺失造成解码饥饿与前端瓶颈;现有基于前端关键性的 L2 替换策略中关键行的关键性行为高度动态,仅约 28.32% 能保持。
方法
将分支历史作为上下文信息改进关键指令行检测,并基于指令行重用距离随分支历史变化的观察,设计同时考虑关键性与重用行为的 L2 替换策略 ICARUS。
评估
在 12 个数据中心应用上对比 TPLRU 与 EMISSARY,测量性能提升,并在不同 L1I/L2 缓存容量及硬件预取器存在的情况下验证鲁棒性。
原文摘要(Abstract)

Datacenter applications with huge code footprints suffer from front-end CPU bottlenecks even with a decoupled front-end. These applications are composed of complex system stacks with subtle interdependencies. One of the primary contributors to the front-end bottleneck is instruction misses at L2, which cause decode starvation. State-of-the-art L2 cache replacement policies, such as EMISSARY, utilize front-end criticality to identify instruction lines that cause decode starvation and attempt to keep those critical lines in L2. We observe that only 28.32% of the critical lines retain their criticality behavior, and a significant fraction of the critical instruction lines show dynamic behavior. We propose ICARUS, an L2 replacement policy that incorporates branch history as context information to improve critical instruction line detection. We observe that the reuse distance of instruction lines varies based on the branch history that led to the instruction fetch. Next, we enhance the L2 replacement policy by considering both criticality and the reuse of instruction lines at L2, as we observe that the reuse behavior of critical lines differs from that of non-critical lines. On average, across 12 datacenter applications, ICARUS outperforms Tree-based Pseudo LRU (TPLRU) by 5.6% and as high as 51%. The state-of-the-art replacement policy, EMISSARY, on the other hand, provides an improvement of 2.2% over TPLRU. We demonstrate the robustness of ICARUS across various L1I and L2 cache sizes, as well as its effectiveness in the presence of hardware prefetchers.

链接与引用

DOI 原文 · PDF(开放获取) · DBLP

BibTeX
@inproceedings{KalbandeD0P26,
  title = {ICARUS: Criticality and Reuse based Instruction Caching for Datacenter Applications},
  author = {Vedant Kalbande and Hrishikesh Jedhe Deshmukh and Alberto Ros and Biswabandan Panda},
  booktitle = {ASPLOS},
  year = {2026},
  doi = {10.1145/3779212.3790175}
}