一句话：提出 PDIP，一种与 FDIP 协同的指令预取器，仅针对真正影响前端性能的 I-Cache 缺失进行预取。
现代服务器工作负载代码足迹大，容易因指令缓存容量缺失造成前端瓶颈。现代处理器中的 FDIP 已能容忍 BPU 预测路径上的大量缺失，但仍存在显著前端停顿。以往指令预取研究并非面向 FDIP 处理器设计，其唯一目标是减少 I-Cache 缺失，而 FDIP 处理器本身以容忍缺失为目标。为使预取器与 FDIP 协同，需要识别哪些缓存缺失真正影响前端性能（未被 FDIP 完全隐藏），并只针对这些缺失进行预取。本文提出 PDIP（Priority Directed Instruction Prefetching），按优先级定向预取这些关键缺失。摘要未报告具体实验数据。
Modern server workloads have large code footprints which are prone to front-end bottlenecks due to instruction cache capacity misses. Even with the aggressive fetch directed instruction prefetching (FDIP), implemented in modern processors, there are still significant front-end stalls due to I-Cache misses. A major portion of misses that occur on a BPU-predicted path are tolerated by FDIP without causing stalls. Prior work on instruction prefetching, however, has not been designed to work with FDIP processors. Their singular goal is reducing I-Cache misses, whereas FDIP processors are designed to tolerate them. Designing an instruction prefetcher that works in conjunction with FDIP requires identifying the fraction of cache misses that impact front-end performance (that are not fully hidden by FDIP), and only targeting them.
@inproceedings{paperbot11243,
title = {PDIP: Priority Directed Instruction Prefetching},
author = {Bhargav Reddy Godala and Sankara Prasad Ramesh and Gilles A. Pokam and Jared Stark and Andre Seznec and Dean Tullsen and David I. August},
booktitle = {ASPLOS},
year = {2024},
doi = {10.1145/3620665.3640394}
}