一句话：提出延迟抽象接口与参数化 HDL Lilac，用类型系统保证参数化设计无结构性冒险，提升硬件集成效率。
硬件设计中，时序依赖输入的模块需使用延迟不敏感（LI）接口，而时序独立时使用延迟敏感（LS）接口性能最佳；但集成外部生成的 LS 模块常被迫用 LI，带来纯开销。论文提出延迟抽象（LA）接口：在设计期提供 LI 的时序适应性，并通过输出参数让子模块向父模块返回值，在 elaboration 时按参数编译为高效 LS 接口。为处理参数化复杂性，作者实现 Lilac——一种参数化 HDL，其类型系统跟踪参数对时序行为的影响，并形式化保证任一参数化实例无结构性冒险。评估用其实现参数化设计并集成外部工具生成模块，相比 LI 实现减少 26–33% 芯片资源，最大频率提升 6.8%。
Hardware designs must use latency-insensitive (LI) interfaces when timing is input-dependent. When timing is input-independent, designs should use latency-sensitive (LS) interfaces for maximum performance. However, designs commonly use LI interfaces to integrate with externally generated LS modules--from, e.g., IP generators, high-level synthesis, or domain specific languages. In every fully integrated design, such uses of LI represent pure overhead. The challenge is that generators can dramatically change timing interfaces of the modules to meet performance objectives, and LI interfaces act as a useful design abstraction and enable timing adaptation. We define latency-abstract (LA) interfaces, a new design abstraction, which provide the timing adaptability of LI interfaces at design-time and the efficient integration of LS interfaces. LA interfaces use output parameters, a novel compile-time mechanism for child modules to return values parent modules, to abstract and encapsulate timing behaviors at design time. During design elaboration, LA interfaces are compiled into efficient LS interfaces based on parameter values. While an attractive option, LA interfaces inherit the complexities of parameterized hardware design: the user must reason how parameters influence timing behaviors of modules and ensure that designs adapt to interface changes. To address this challenge and demonstrate the utility of LA interfaces, we design Lilac, a parameterized HDL that uses a type system track the influence of parameters on timing behaviors and formally guarantee that every parameterization of an LA design results in a circuit without structural hazards. We demonstrate Lilac's efficacy by using it to implement parameterized designs and integrate designs generated from external tools. We show that LA designs use 26--33% fewer chip resources and achieve 6.8% better maximum frequencies than comparable LI implementations.
DOI 原文 · arXiv · PDF（开放获取） · DBLP
@inproceedings{NigamGLZBS26,
title = {Parameterized Hardware Design with Latency-Abstract Interfaces},
author = {Rachit Nigam and Ethan Gabizon and Edmund Lam and Carolyn Zech and Jonathan Balkind and Adrian Sampson},
booktitle = {ASPLOS},
year = {2026},
doi = {10.1145/3779212.3790199}
}