一句话：提出周期级剖析器 Petal，让加速器设计语言的程序员理解编译器决策如何影响生成硬件的性能。
加速器设计语言（ADL）能把高层程序编译为硬件单元，但其编译器需跨越高层语义与周期级调度之间的巨大语义鸿沟，并依赖复杂启发式，导致生成硬件的性能难以预测、问题难以定位。作者认为这种不可预测性是该问题的固有属性，编译器无法做到完美，因此应转而构建帮助程序员理解编译器的工具。本文提出 Petal：它在 Calyx 中间语言代码中插桩探针，分析寄存器传输级仿真的 trace，将事件映射回 Calyx 高层控制构造以判定各构造的活跃时刻，进而生成逐周期的调用树 trace；最后利用 ADL 编译器产生的元数据构造 ADL 级 profile。案例研究表明，Petal 的周期级 profile 能识别现有加速器设计中的性能问题，并引导开发者完成编译器未能自动完成的优化，其中一个应用的总周期数减少了 46.9%。
Accelerator design languages (ADLs), high-level languages that compile to hardware units, help domain experts quickly design efficient application-specific hardware. ADL compilers optimize datapaths and convert software-like control flow constructs into control paths. Such compilers are necessarily complex and often unpredictable: they must bridge the wide semantic gap between high-level semantics and cycle-level schedules, and they typically rely on advanced heuristics to optimize circuits. The resulting performance can be difficult to control, requiring guesswork to find and resolve performance problems in the generated hardware. We conjecture that ADL compilers will never be perfect: some performance unpredictability is endemic to the problem they solve. In lieu of compiler perfection, we argue for compiler understanding tools that give ADL programmers insight into how the compiler’s decisions affect performance. We introduce Petal, a cycle-level profiler for ADLs that compile to the Calyx intermediate language (IL). Petal instruments the Calyx code with probes and then analyzes the trace from a register-transfer-level simulation. It then maps the events in the trace back to high-level control constructs in the Calyx code to determine when each construct was active. Petal processes that information into a trace of call trees , each representing active events in a specific cycle and their relationships. Lastly, Petal uses metadata generated by the ADL compiler to construct an ADL-level profile. Using case studies, we demonstrate that Petal’s cycle-level profiles can identify performance problems in existing accelerator designs. We show that these insights can also guide developers toward optimizations that the compiler was unable to perform automatically, including a reduction by 46.9% of total cycles for one application.
@article{paperbot12103,
title = {Understanding Accelerator Compilers via Performance Profiling},
author = {Ayaka Yorihiro and Griffin Berlstein and Pedro Pontes García and Kevin Laeufer and Adrian Sampson},
journal = {Proceedings of the ACM on Programming Languages},
volume = {10},
number = {OOPSLA2},
year = {2026},
doi = {10.1145/3839509}
}