一句话：提出 DSL 与事件追踪框架 HT，通过地址布局指定微架构效应并连接软硬件事件，支持处理器性能分析。
现代处理器性能分析面临两大难题：难以构造精确限定微架构假设的性能测试，也难以将大量底层硬件事件映射回被测程序。本文提出统一的编程语言方法并实现原型框架 HT。针对测试构造，作者观察到许多微架构效应由特定软件地址布局触发，因而设计 DSL，将程序的微架构效应规约与功能行为分离，并借助 SMT 求解器自动计算合适的指令与数据布局。针对可观测性，作者系统地将高层软件模式与原始硬件仿真输出关联，引入灵活的事件追踪构造，从单周期底层事件日志构建定制的多周期高层事件，作为软件执行模式与底层硬件事件之间的桥梁。作者在生产级开源 RISC-V 处理器香山（XiangShan）上通过三个案例研究展示 HT 的实用性：分析 Zicond 扩展的性能影响、复现微架构攻击、刻画解释型语言 Lua 的分支预测行为。
Analyzing, understanding, and validating the performance of modern processors present significant challenges. These stem from two primary issues. First, it is difficult to construct “performance tests” that can test precisely scoped hypotheses about microarchitectural behavior. Second, it is difficult to make sense of performance measurements: hardware teams see too many low-level events that they struggle to map back to the tested programs, and software developers and security researchers can only observe coarse-grained performance counters. This paper addresses both challenges with a unified programming language approach that we prototype in a framework named HT. To overcome the test-construction problem, our insight is that a broad range of microarchitectural effects are triggered by a specific software address layout. We introduce a DSL that enables specifying desired microarchitectural effects of a program through specifying its address layout, separately from its functional behavior. This separation is achieved using an SMT solver to compute a suitable instruction and data layout. To overcome the observability challenge, we systematically link high-level software patterns down to raw hardware simulation outputs. We introduce flexible event-tracing constructs designed to construct custom, multi-cycle higher-level events from (single-cycle) low-level event logs, effectively acting as the bridge that connects software execution patterns to low-level hardware events. We demonstrate HT’s utility on XiangShan, a production-grade open-source RISC-V processor, through three case studies: analyzing the performance impact of the Zicond RISC-V extension, reproducing subtle microarchitectural attacks, and characterizing the branch prediction behavior of Lua, an interpreted language.
@article{paperbot12105,
title = {A Language Approach to Fine-Grained Microarchitectural Observation},
author = {Guokai Chen and Sergi Soler Arrufat and Clément Pit-Claudel and Thomas Bourgeat},
journal = {Proceedings of the ACM on Programming Languages},
volume = {10},
number = {OOPSLA2},
year = {2026},
doi = {10.1145/3839486}
}